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Chip Assembly Routing
The Virtuoso© chip assembly routing flow lets you route a top-level design that has macro instances, I/O pads, devices, and standard cells. It consists of a series of tasks to quickly and automatically generate routed layouts that are constraint compliant and LVS correct, and follow DRCs as captured in the Virtuoso technology file.
This chip assembly routing flow helps circuit and layout designers who are familiar with routing flows on mature nodes for their designs as well as for CAD teams that support such designs. The target designs for this flow are top-level designs.
For chip assembly routing, you use the Routing assistant. This assistant is available in the Layout MXL cockpit.
You can use environment variables to change the value of many aspects of the environment either for an individual design session or until you change the value of the variable again.
Related Topics
Environment Setup for Chip Assembly Routing Flow
Chip Assembly Routing Configuration
Routing Assistant User Interface for Chip Assembly Routing Flow
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