Bus Annotation in Abstract Generator

Bus Annotation for Abstract Generator improves the interoperability between Virtuoso and Innovus. You can directly import the library elements created inside Abstract Generator to Innovus.

In OpenAccess, cellview data of a library element created by applications such as Abstract Generator (AG) usually consists of explicit scalar bits (A<0>, A<1>) corresponding to a vector bus terminal (A<0:1>). This is because pins and corresponding pinFigs have to be created on each bit with specified layer and shape for physical connectivity.

When OA cellview of library element is used by applications like Innovus and verilog2oa, as shown in the following two figures, the order of bits on a bus, which can be either ascending (0:1) or descending (1:0), is important. This cannot be inferred from scalar bits present in the OA data of the library element.

For this flow to work, run Verilog Annotate on the library elements before data is used in Innovus. The verilogAnnotate annotates the vector bus terminal information on the OA cellview of the library element. Running verilogAnnotate requires a corresponding interface definition in verilog format of the module corresponding to the library element. For each library element, a verilog stub file is created as described in the following figure. The verilog stub file is created from corresponding schematics and symbol definitions by using the Create – Cellview – From Cellview commands followed by Verilog Annotate. However, creating verilog stubs and running verilogAnnotate is a time consuming process.

In Virtuoso XL, while creating an abstract, an input logical view option can be used to specify the symbol, schematic, verilog, or .liberty (.lib) from which bus definition is extracted. The vector terminal information is directly added to the OA cellview of the library element by the Abstract Generator engine and there is no need to generate the verilog stub file and run verilogAnnotate.