Restrictions for Signal and Power Pin Geometry

The following restrictions apply to setting signal and power pin geometry:

• If there is a metal0 local interconnect layer, it would have to be entered manually.
• If two layers connect by overlap, specify a layer pair (M0 M1).
• It is not permitted to specify (layer1 layer2 via12) and (layer1 layer2) and so on at the same time.

For example,

(metal1 metal2 via12) (metal2 metal3 via23)
(poly metal1 cont)
(pdiff metal1 cont)
(ndiff metal1 cont)
(poly li)
(ndiff li)
(pdiff li)

This means,

• metal1 connects to metal2 through via12 layer
• metal2 connects to metal3 through via23 layer
• poly connects to metal1 through cont layer
• pdiff connects to metal1 through cont layer
• ndiff connects to metal1 through cont layer
• poly connects to local interconnect by overlap
• ndiff connects to local interconnect by overlap
• pdiff connects to local interconnect by overlap

Related Topics

Running Step Extract Form

Specifying Connectivity Information in Designs

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