Support for Overridden and Instance Terminals

Abstract Generator supports overridden terminals and instance terminals in block domain. The Abstract Generation commands do not create overriding terminals or instance terminals. However, these overridden terminals and instance terminals can be present in OpenAccess data coming from Innovus or any other application using OA. Therefore, the support is required for interoperability between Innovus and Virtuoso.

The behavior of commands in Abstract Generator is given as follows:

• The commands processing pins and pin figures on overridden terminals and instance terminals, of master instance having pins and pin figures, should consider overridden terminal and instance terminal as a normal block domain terminal or instance terminal, without any difference in the behavior. For example, the Pin Optimize command should optimize pins on overridden terminal and instance terminal.
• The commands involving change of signal type should ensure that nets connected to overriding terminals and instance terminals can only be of signal type power, ground, tieHi, tieLo, and tieOff.
  In Abstract Generator, you can set the signal type for terminals only as signal, clock, power, ground, or analog. If pins on the layout and the terminals for the same pins have another signal type, such as reset, the signal type value is retained as reset in the abstract view as well.
• The commands processing (deleting) empty nets should be careful because a net may be empty only in the block domain and may have a terminal/instance terminal in module domain. Therefore, the net is not empty as corresponding terminals and instance terminals are hidden in the block domain.

Command related to terminals and instance terminals is Abstract Generate.

The tieHigh, tieLow, tieOff, power, ground and signal nets specified in verilog can be implemented in block domain using any physical-only net. The example for this is given as follows:

/ Verilog file for cell "top_level" view "layout"

// Language Version: 2001

module top_level (

A,

B,

C,

D,

Z

);

input A;

input B;

input C;

input D;

input _IN;

output Z;

output _OUT;

wire net1;

assign _OUT = 1’b1;

assign _IN = 1’b0;

block3 I1 ( .A(A), .B(B), .C(C), .Y(net1), .Z(1’b1));

block I2 ( .A(net1), .B(1’b1), .C(D), .Z(Z), .„nd! (1’b0), .\vdd! (1’b1));

endmodule // top_level

In the mentioned example, observe the following in the connectivity:

• The terminals _IN and _OUT are connected to tie0 and tie1 nets, respectively.
• The instance terminals corresponding to I1/Z and I2/B are connected to tie.
• The instance terminals corresponding to I2/vdd! and I2/gnd! are connected to tie1 and tie0 nets, respectively

It is significant to understand that verilog designer has no clue how 1’b1 (tieHi) and 1’b0 (tieLow) nets will be implemented in the layout or block domain. It depends on the block designer to choose any physical only net to implement 1’b1 and 1’b0. For example, the following array of nets can be used to implement.

• _IN and I2/gnd! (tie0) to be implemented by net VSS (physical only).
• _OUT and I2/vdd! (tie1) to be implemented by net VDD (physical only).
• I1/Z and I2/B (tie1) to be implemented by net INTERNALVDD (physical only).

The following changes in the block domain will have to be made.

• Hide _IN _OUT terminals.
• Hide instance terminals I2/gnd!, I2/vdd!, I1/Z and I2/B.
• Create overriding terminals and overriding instance terminals with same names to implement them using the above mentioned physical only nets.

Related Topics

Flows Supported by Abstract Generator

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