Product Documentation
Virtuoso Technology Data Constraints Reference
Product Version IC23.1, November 2023

minDiffNetSpacing

spacings(
( minDiffNetSpacing tx_layer 
 f_spacing 
)
) ;spacings

Specifies the minimum spacing between shapes on nets at different voltage levels on the specified layer.

This constraint applies to wells, transistors, and devices. When two geometries, typically two "NWell" shapes, are at different voltages, a larger spacing is required between the two shapes. The larger spacing prevents potential leakage problems through the substrate.

Values

tx_layer

The layer on which the constraint is applied.

Type: String (layer and purpose names) or Integer (layer number)

f_spacing

The spacing between two shapes that are at different voltage levels must be greater than or equal to this value.

Parameters

None

Example

The following spacing requirement must be satisfied if a voltage difference exists between two nets on a layer:

spacings(
    ( minDiffNetSpacing "Metal1" 
     1.0
)
( minDiffNetSpacing "Metal2"
techParam("mindiffnetspace1")
)
) ;spacings

Return to top
 ⠀
X