CDL Out interprets a signal that ends with a ! as a global signal. The signal name appears in the .global and .pin statements. If the global signal is associated with a component, the signal does not appear in the I/O signal list of a subcircuit definition.
Do not use global signals with a hierarchical input connector unless the schematic is the top-level block of the design. If you use the global signal with a hierarchical input connector, the signal appears in the I/O signal list of a subcircuit definition and creates warnings when you run LOGLVS. Assign wire or label connections directly to instances in the schematic (for example, when you use globals with components.)
For nmos, pmos, and cap devices in the Cadence Library, by default a substrate connection to power or ground is made in the netlist. To override the VDD and GND defaults for these connections, include the following declarations in the .simrc file:
hnlCDLNMOSBulkNetName="cvss!"
hnlCDLPMOSBulkNetName="cvdd!"
hnlCDLCAPBulkNetName="dvss!"
In this example, cvss is the bulk connection for the nmos device, cvdd is the bulk connection for the pmos device, and dvss is the bulk connection for the cap device. The signals appear as CVSS!, CVDD!, and DVSS! in the netlist.
Just like in the schematic where the global signal names are suffixed with !, the global signal names in the output CDL netlist file also end with !.