The lowest levels of the schematic must contain primitives that CDL Out recognizes; for example, transistors, resistors, and capacitors. You must extract and save all levels of the schematic hierarchy before you netlist your design using CDL Out.
If you work on a circuit-level schematic and you create a circuit cell, which uses different parameter values for different instances of that cell, parameter inheritance is important. For example, you might generate an inverter in your library and use it with 1X drive strength in one cell and with 2X drive strength in another. To ensure that the correct parameter values are passed to the appropriate instances, pass them through the hierarchy.
When you use hierarchical netlisting and parameter inheritance at the same time, special limitations apply. For information about these limitations, see How CDL Out Translates Parameters.
How CDL Out Translates Parameters?