Fault simulations in ADE Assembler provide the capability to run defect-oriented tests on analog IC designs. These tests allow you to evaluate the ability to eliminate a die with manufacturing defects and resulting test escapes that cause field failures. It can also be used to optimize wafer test, reducing the number of tests required to achieve the target defect coverage by eliminating over-testing and potentially reducing the number of tests.
The following topics describe the important tasks you can perform for fault simulation:
- How to inject faults in a design?
- How to preview the fault list for simulation?
- How does fault sampling affect the fault list?
- How to implement automatic fault dropping during simulation run?
- Is it possible to merge results from multiple fault simulations?
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