Product Documentation
Virtuoso ADE SKILL Reference
Product Version IC23.1, November 2023

asiAddVerilogArgs

asiAddVerilogArgs( 
o_session
t_verilogArg
)
=> t_verilogArg

Description

For a mixed-signal simulation, this method lets you change the list of arguments that are sent to the Verilog-XL simulator with the -slave option.

These arguments are the options from the Verilog Options form. Typically, you use this function to add the +vmxcconfig.vmx option.

Note for Integrators: This function is defined as a method. You can overload this method for your simulator class, as shown in the example for integrators.

Arguments

o_session

Simulation session object.

t_verilogArg

Arguments (or options) to send to the Verilog-XL simulator with the -slave option.

Value Returned

t_verilogArg

Returns the arguments (or options) that are sent to Verilog-XL with the -slave option.

Examples

defmethod( asiAddVerilogArgs ( ( session XYZ_session ) verilogArg )
    sprintf( verilogArg "%s +vmxcconfig.vmx"  verilogArg )
)

Adds +vmxcconfig.vmx to the list of Verilog-XL arguments for the XYZ simulator class.


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