schPinListToVerilog

schPinListToVerilog( 
t_libName 
t_cellName 
t_viewName 
g_pinList 
)
=> t / nil

Description

Generates a Verilog HDL cellview from a pin list. The generated Verilog HDL cellview can be used with the Verilog integration.

Arguments

t_libName	Library containing the Verilog HDL cellview to generate from the pin list; must be enclosed in quotation marks.
t_cellName	Cell containing the Verilog HDL cellview to generate from the pin list; must be enclosed in quotation marks.
t_viewName	View containing the Verilog HDL cellview to generate from the pin list; must be enclosed in quotation marks.
g_pinList	Terminal and property information to use in generating the target Verilog HDL cellview.

Value Returned

t	Generated a Verilog HDL cellview from a pin list.
nil	Could not generate Verilog HDL cellview.

Examples

schPinListToVerilog( "myLib" "myDesign" "functional" pinList )

where

pinList = ‘( nil ports ((nil name "a" direction "input" )
    ( nil name "b" direction "input" )
    ( nil name "c" direction "output" )
    )
)

Generates the following Verilog module:

module myDesign ( "a", "b", "c" );
    input a;
    input b;
    output c;
endmodule

The pin list format represents all the terminals and properties and is stored in a disembodied property list with the following format:

g_pinList = ‘(nil ports portList
    [prop proplist] )
portlist = (termDef termDef...termDef)
termDef = (nil name "termName"
    direction "termDir"
    [prop propList]
    [pins termPins]
    )
proplist = (nil propName propValue
    propName propValue
    ...
    )
termPins = (pinDef pinDef...pinDef)
pinDef =  (nil name "pinName"
    [accessDir "accessDir"])

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