schSRC
schSRC(d_cvId) =>l_result
Description
Runs the schematic rules checker (SRC) on a specified cellview.
You can set the schematic rules checker rules by
- Specifying options on the Setup Schematic Rules Checks options form
-
Calling
schSetEnvto set the schematic environment variable that controls a check -
Specifying values for the schematic environment variables in your
.cdsenvfile
You can set the values for the schematic environment variables that control the logical, physical, and name checks. For most of the schematic environment variables that control checks, the three possible values are ignored, warning, and error. These three values are collectively known as the check severity.
-
When you set the check severity value for a variable to
ignored, the system does not perform the check associated with that variable. -
When you set the check severity value for a variable to
warning, the system marks any violations discovered during the check as warnings. You can save a design that contains warnings, and you can simulate a design that contains warnings. Nevertheless, you should review the warnings before proceeding. -
When you set the check severity value for a variable to
error, the system marks any violations discovered during the check as errors. You can save a design that contains errors, but you cannot simulate the design simulation until you correct the errors.
Can be used only on an editable schematic.
Arguments
Value Returned
|
A list containing the number of errors and warnings, respectively. |
Examples
Runs the schematic rules checker on the given cellview and extracts the number of errors and warnings from the result.
result = schSRC( cvId )
numErrors = car( result )
numWarns = cadr( result )
Sets the severity of the three checks—srcUnconnectedWires, srcVerilogSyntax, and srcVHDLSyntax—and then invokes the schematic rules checker.
schSetEnv( "srcUnconnectedWires" "ignored" )
schSetEnv( "srcVerilogSyntax" "error" )
schSetEnv( "srcVHDLSyntax" "ignored" )
result = schSRC( cvId )
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