schVerilogToPinList

schVerilogToPinList( 
t_libName 
t_cellName 
t_viewName 
)
=> g_pinList / nil

Description

Generates a pin list from a Verilog HDL cellview.

Arguments

t_libName	Library containing the Verilog HDL cellview; must be enclosed in quotation marks.
t_cellName	Cell containing the Verilog HDL cellview; must be enclosed in quotation marks.
t_viewName	View containing the Verilog HDL cellview; must be enclosed in quotation marks.

Value Returned

g_pinList	Terminal and property information in the form of a pin list, generated from the source Verilog HDL cellview.
nil	Unsuccessful.

Examples

Returns the pin list representing the source Verilog HDL cellview.

pinList = schVerilogToPinList( "myLib" "myDesign" "symbol" )

The pin list format represents all the terminals and properties and is stored in a disembodied property list with the following format:

g_pinList = ‘(nil ports portList
    [prop proplist] )
portlist = (termDef termDef...termDef)
termDef = (nil name "termName"
direction termDir
    [prop propList]
    [pins termPins]
    )
proplist = (nil propName propValue
    propName propValue
    ...
    )
termPins = (pinDef pinDef...pinDef)
pinDef =  (nil name "pinName"
    [accessDir "accessDir"])

See the your_install_dir/tools/dfII/samples/local/schConfig.il file for usage of schVeriloglToPinList in the schViewToPinListReg list of translation functions.

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