Support for Verilog-A Models

The Cadence® Verilog®-A language is the analog subset of the Verilog-AMS language. With Verilog-A, you can create and use modules that describe the high-level behavior of components and systems. The Verilog-A language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. With the analog statements of Verilog-A, you can describe a wide range of conservative systems and signal-flow systems, such as electrical, mechanical, fluid dynamic, and thermodynamic systems. To describe a system, you must specify both the structure of the system and the behavior of its components.

The following is the syntax to invoke a Verilog-A model:

Spectre Syntax

ahdl_include "[filepath]veriloga_file.va"

SPICE Syntax

.hdl [filepath]veriloga_file.va

Related Topics

Cadence Verilog-A Language Reference