Post-layout Simulation Methodologies

There are three post-layout simulation methodologies:

Flat RC Netlist File
A flat netlist containing many elements and devices. One example is to directly include the DSPF file. Another example is the netlist from the Quantus QRC extracted view, which is often used in Virtuoso® ADE Explorer or Virtuoso® ADE Assembler.
Hierarchical RC Netlist File
A netlist file that contains a hierarchy of extracted subcircuits.
Backannotation of Parasitic Files
DSPF/SPF/DPF files containing parasitic information. This methodology combines the parasitic information with the pre-layout netlist through backannotation. It enables Spectre FX to automatically plug in the parasitic elements during the simulation.
The SPEF format is currently not supported in this release.