Product Documentation
Spectre Circuit Simulator Reference
Product Version 23.1, September 2023

Alter Group (altergroup)

Description

The altergroup statement changes the values of any modifiable model, instance or netlist parameter for any analyses that follow. Within an alter group, you can specify model statements, instance statements, parameter statements and options statements (only supports temp, tnom, and scale). These statements should be bound within braces. The opening brace is required at the end of the line defining the altergroup. Altergroups cannot be specified within subcircuits. The following statements are not allowed within altergroups (analyses, export, paramset, save, and sens).

Within an altergroup, each device (instance or model) is first set to default and then the device parameters are updated. For netlist parameters, the expressions are updated and evaluated.

For subcircuit within altergroup, all instances of the subcircuits are modified when running altergroup. There are strict checks that do not allow changes to topology.

You can include files into the altergroup and can use the simulator lang=spice directive. See spectre -h include for more information. A model defined in the netlist should have the same model name and primitive type (bsim2, bsim3, bjt) in the altergroup. An instance defined in the netlist, should have the same instance name, terminal connections, and primitive type. For model groups, you can change the number of models in the group. However, you cannot change from a model to a model group and vice versa. See spectre -h bsim3v3 for details on model groups.

Syntax

Name altergroup parameter=value ...

Parameters

annotate

Degree of annotation. Possible values are no and title.

title

Altergroup title.

Example

FastCorner altergroup {
        parameters p2=1 p3=p1+2
        myopt options temp=27 
        model myres resistor r1=1e3 af=1 
        model mybsim bsim3v3 lmax=p1 lmin=3.5e-7 
        m1 (n1 n2 n3 n4) mybsim w=0.3u l=1.2u 
}
The list of public devices supported by altergroup is as follows:
angelov    angelov_gan    asm_gan    assert
bht    bht0    bjt    bjt301
bjt500    bjt500t    bjt503    bjt504
bjt504t    bjt505    bjt505t    bjt3500
bjt3500t    bjtd504    bjtd504t    bjtd505
bjtd505t    bjtd3500    bjtd3500t    bsim1
bsim2    bsim3    bsim3v3    bsim4
bsim6    bsimbulk    bsimcmg    bsimimg
bsimsoi    bsimsoi_s    bsource_resistor    capacitor
capq    capsim    cccs    ccvs
dcblock    dcfeed    delta_gate    dio500
diode    diode_cmc    ekv    ekv3
ekv3_nqs    ekv3_r4    ekv3_rf    ekv3_s
fracpole    gaas    hbt    hemt
hisim2    hisim2_va    hisim_diode    hisim_hv
hisim_igbt    hisimhmg    hisimhv_va    hisimsoi
hisimsoi_bt    hisimsoi_fb    hvmos    igbt0
inductor    intcap    iprobe    isource
jfet    jfet100    jfet100q    jfetidg
jfetidgt    jj    juncap    juncap200
juncap_eldo    ldmos    lutsoi    lutsoit
mos1    mos2    mos3    mos40
mos40t    mos902    mos903    mos903c
mos903e    mos903t    mos1101e    mos1101et
mos1102e    mos1102et    mos2002    mos2002e
mos2002et    mos2002t    mos3100    mos3100t
mos11010    mos11010t    mos11011    mos11011t
mos11020    mos11020t    mos11021    mos11021t
mosvar    msline    mutual_inductor    mvsg_gan
nodcap    ovcheck    ovcheck6    pattern
pcccs    pccvs    phy_res    port
print    psitft    psp102    psp102e
psp103    psp103t    psp1020    psp1021
pspnqs102e    pspnqs103    pspnqs1020    pspnqs1021
pvccs    pvcvs    r2    r3
rdiff    resistor    rlck_matrix    spmos
ssim_mbc    tline    tom2    tom3
tom3v1    transformer    ucsd_hbt    utsoi2
vbic    vccs    vcvs    vsource
wprobe    wsource    
The list of public devices not supported by altergroup is as follows:
a2d    atft    bend    bend2
bit    bsource_capacitor    cktrom    conductor
core    corner    cross    curve
d2a    delay    dielectric    ibis_buffer
iswitch    jitterevent    loc    mos0
mos15    mtline    nport    pdbi2dProxy
relay    scccs    sccvs    sprobeport
stackup    step    svccs    svcvs
switch    tee    vswitch    winding
zcccs    zccvs    zvccs    zvcvs

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