Using analogmodel for Model Passing (analogmodel)

Description

analogmodel is a reserved word in Spectre that allows you to bind an instance to different masters based on the value of a special instance parameter called modelname. An instance of analogmodel must have a parameter named modelname, whose string value represents the name of the master this instance will be bound to. The value of modelname can be passed into subcircuits.

The analogmodel keyword is used by the Cadence Analog Design Environment to enable model name passing through the schematic hierarchy.

Sample Instance Statement

name [(]node1 ... nodeN[)] analogmodel modelname=mastername [[param1=value1] ...[paramN=valueN]] 

name	Name of the statement or instance label.
[(]node1...nodeN[)]	Names of the nodes that connect to the component.
analogmodel	Special device name to indicate that this instance will have its master name specified by the value of the modelname parameter on the instance.
modelname	Parameter to specify the master of this instance indicated by mastername. The mastername must either be a valid string identifier or a netlist parameter that must resolve to a valid master name, a primitive, a model, a subckt, or an AHDL module.
param1 param2...	Parameter values for the component. Depending on the master type, these can either be device parameters or netlist parameters. It is optional to specify these parameter values.

Example

//example spectre netlist to illustrate modelname parameter 

simulator lang=spectre 
parameters b="bottom" 
include "VerilogAStuff.va" 

topInst1 (out in) top 
topInst2 (out in) analogmodel modelname="VAMaster" //VAMaster is defined in                                                      "VerilogAStuff.va" 
topInst3 (out in) analogmodel modelname="resistor" //topInst3 binds to a primitive 
topInst4 (out 0) analogmodel modelname="myOwnRes" //topInst4 binds to modelcard                                                     "myOwnRes" defined below
v1 in 0 vsource dc=1

model myOwnRes resistor r=100
subckt top out in 
parameters a="mid" 
x1 (out in) analogmodel modelname=a //topInst1.x1 binds to "mid" 

ends top 

subckt mid out in 

parameters c="low" 
x1 (out in) analogmodel modelname=b //topInst1.x1.x1 binds to "bottom" 
x2 (out in) analogmodel modelname=c //topInst1.x1.x1.x2 binds to "low" 

ends mid 

subckt low out in 

x1 (out in) analogmodel modelname="bottom" //topInst1.x1.x1.x2.x1 binds to
                                             "bottom" 

ends low 

subckt bottom out in 

x1 (out in) analogmodel modelname="resistor" //x1 binds to primitive "resistor"

ends bottom 

dc1 dc 

//"VerilogAStuff.va" 
‘include "constants.h" 
‘include "discipline.h" 
module VAMaster(n1, n2); 
inout n1, n2; 
electrical n1, n2; 
parameter r=1k; 
analog begin 
I(n1, n2) <+ V(n1, n2)/r; 
end 
endmodule 

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