Verilog-A Usage and Language Summary (veriloga)
Description
Verilog-A is an analog hardware description language standard from Open Verilog International. It enables analog circuit behavior to be described at a high level of abstraction. Behavioral descriptions of modules and components may be instantiated in a Spectre netlist along with regular Spectre primitives.
Verilog-A descriptions are written in files different from the Spectre netlist file. These descriptions are written in modules (see the module alpha below). To include a module in the Spectre netlist, first add the line ahdl_include "VerilogAfile.va to the Spectre netlist file (where, VerilogAfile.va is the name of the file in which the required module is defined). The module is instantiated in the Spectre netlist in the same manner as Spectre primitives, for example:
name (node1 node2) alpha arg1=4.0 arg2=2
This instantiates an element alpha, which has two nodes and two parameters.
AHDL Linter can be used to improve Verilog-A model quality. It can help to avoid potential convergence or performance problems, and to improve model accuracy, reusability and portability. Refer to the Verilog-A Language Reference manual for more information.
Verilog-A simulation performance has been improved by compiling the Verilog-A modules. This is explained in more detail in the Verilog-A compilation section below.
Module Template
The following is a Verilog-A module template
include "discipline.h"
include "constants.h"
module alpha( n1, n2 );
electrical n1, n2;
parameter real arg1 = 2.0;
parameter integer arg2 = 0;
real local;
// this is a comment
analog begin
@ ( initial_step ) begin
// performed at the first timestep of an analysis
end
// module behavioral description
V(n1, n2) <+ I(n1, n2) * arg1;
@ ( final_step ) begin
// performed at the last time step of an analysis
end
end
endmodule
Verilog-A Compilation
The first time a verilogA file is used in simulation, Spectre performs a one-time compilation step. Following the initial compilation, recompilation is performed only if the Verilog-A source is changed.
The compiled C code flow stores the compiled shared objects in a database on the disk for the simulation to use. The shared objects are stored in a directory named ahdlSimDB. By default, this database is created in the current working directory and given a name created by appending .ahdlSimDB to the circuit name. You can specify an alternative location for ahdlSimDB by setting the CDS_AHDLCMI_SIMDB_DIR environment variable to the path of a directory, as follows:
setenv CDS_AHDLCMI_SIMDB_DIR /projects/ahdlcmiSimDirs
If the path is writable, adhlSimDB is created there. If the path is not writable or does not exist, an error is reported.
To store compiled objects, use a second type of database, named ahdlShipDBs. To create such databases, set the CDS_AHDLCMI_SHIPDB_COPY to YES, as follows:
setenv CDS_AHDLCMI_SHIPDB_COPY YES
In this case, an ahdlShipDB is created for each Verilog-A file in the directory that contains the Verilog-A files, if the directory is writable. If the directory is not writable, no ahdlShipDBs are created for the modules in the Verilog-A file that is being processed.
If the CDS_AHDLCMI_SHIPDB_DIR environment variable (or the equivalent, but obsolete, CDS_AHDLCMI_DIR variable) is also set to a writable path, the ahdlShipDB database is created there and shared by all the Verilog-A files used for simulations that are run while this environmental variable is set. If the CDS_AHDLCMI_SHIPDB_DIR is not set to a writable path or the path does not exist, a warning is reported and ahdlShipDBs are not created.
The reuse of Verilog-A compiled library can also be achieved by command-line options, refer to the usage of the Spectre command-line options: -ahdlshipdbdir and -ahdlshipdbmode.
Language Summary
The following provides a summary of the Verilog-A analog hardware description language. For more information refer to Verilog-A Reference Manual.
Analog Operators/Waveform Filters
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ddt(x <,abstol> )
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Differentiate x with respect to time.
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idt(x, ic <, assert <, abstol> > )
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Integrate x with respect to time. Output = ic during dc analysis and when assert is 1.
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idtmod(x <, <ic <, modulus <, offset <, abstol> > > > )
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Circular Integration of x with respect to time. Output = ic during DC analysis. Integration is performed with given offset and modulus, if specified.
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transition(x <, delay <, trise <, tfall <, timetol> > > >)
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Specify details of signal transitions. For efficient simulation, it is recommended that x not be a continuous signal, that is, a function of a probe. See the Verilog-A manual for further explanation of this issue.
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slew(x <, SRpos <, SRneg>>)
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Model slew rate behavior.
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delay(x, time_delay, max_delay)
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Response(t) = x(t - time_delay).
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zi_nd(x, numer, denom, period, < ttransition <,sample offset time > )
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z-domain filter function, numerator-denominator form.
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zi_zd(x, zeros, denom, period, < ttransition <,sample offset time > )
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z-domain filter function, zero-denominator form.
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zi_np(x, numer, poles, period, < ttransition <,sample offset time > )
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z-domain filter function, numerator-pole form.
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zi_zp(x, zeros, poles, period, < ttransition <,sample offset time > )
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z-domain filter function, zero-pole form.
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laplace_nd(x, numer, denom, <, abstol > )
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s-domain filter function, numerator-denominator form.
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laplace_zd(x, zeros, denom, <, abstol > )
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s-domain filter function, zero-denominator form.
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laplace_np(x, numer, poles, <, abstol > )
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s-domain filter function, numerator-pole form.
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laplace_zp(x, zeros, poles, <, abstol > )
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s-domain filter function, zero-pole form.
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Built-In Mathematical Functions
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abs(x)
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Absolute value
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exp(x)
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Exponential if x < 80
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ln(x)
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Natural logarithm
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log(x)
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Log base 10
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sqrt(x)
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Square root
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min(x,y)
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Minimum
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max(x,y)
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Maximum
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pow(x,y)
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x to the power of y
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Noise Functions
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white_noise( power <, tag > )
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Generates white noise with given power. Noise contributions with the same tag are combined for a module.
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flicker_noise( power, exp <, tag > )
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Generates pink noise with given power at 1 Hz that varies in proportion to 1/f^exp. Noise contributions with the same tag are combined for a module.
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noise_table( vector <, tag > )
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Generates noise where power is determined by linear interpolation from the given vector of frequency-power pairs. Noise contributions with the same tag are combined for a module.
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AC Analysis Stimuli
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ac_stim( <analysis_name <, mag <, phase > > > )
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Small signal source of specified magnitude and phase in radians, active for given analysis.
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Analog Events
Analog events must be contained in an analog event detection statement; @(analog_event) statement.
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cross(x, direction <, timetol <, abstol <, enable >>>)
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Generates an event when x crosses zero.
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above(x <, timetol <, abstol <, enable >>>)
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Generates an event when x becomes greater than or equal to zero. An above event can be generated and detected during initialization. By contrast, a cross event can be generated and detected only after at least one transient time step is complete.
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timer(start_time <, period <, timetol <, enable >>> )
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Set (optionally periodic) breakpoint event at time = start_time.
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initial_step< ( arg1 <, arg2 <, etc... > > )
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Generate an event at the initial step of an analysis. arg1, arg2, and so on. Examples of analyses strings are "dc", "tran", "ac", "pss", "noise", "pdisto", "qpss", "pac", "pnoise", "pxf", "sp", "tdr", "xf", "envlp", "psp", "qpsp", "qpac", "qpnoise", "qpxf", "static", "ic", and so on.
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final_step< ( arg1 <, arg2 <, etc... > > )
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Generate an event at the final step of an analysis. arg1, arg2, and so on. Examples of analyses strings are "dc", "tran", "ac", "pss", "noise", "pdisto", "qpss", "pac", "pnoise", "pxf", "sp", "tdr", "xf", "envlp", "psp", "qpsp", "qpac", "qpnoise", "qpxf", "static", "ic", and so on.
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Timestep Control
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bound_step(max_step)
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Limit timestep, (timestep <= max_step).
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last_crossing(x, direction)
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Return time when expression last crossed zero in a given direction.
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discontinuity(n)
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Hint to simulator that discontinuity is present in nth derivative.
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Simulator IO Functions
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$display(argument_list)
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Print data to stdout. Formatting strings may be interspersed between arguments/data.
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$fdisplay(fptr, argument_list)
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Print data to a file. Formatting strings may be interspersed between arguments/data.
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$strobe(argument_list)
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Print data to stdout. Formatting strings may be interspersed between arguments/data.
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$fstrobe(fptr, argument_list)
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Print data to a file. Formatting strings may be interspersed between arguments/data.
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$fscanf(fptr, "format string" <, arguments>)
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Read data from a file
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$fopen("filename", mode)
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Open a file for reading/writing
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$fclose(fptr)
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Close a file
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$finish<(n)>
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Finish the simulation
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$stop<(n)>
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Stop the simulation
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Simulator Environment Functions
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$realtime
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Returns current simulation time
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$temperature
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Returns ambient simulation temperature (K)
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$vt
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Returns thermal voltage
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$vt(temp)
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Returns thermal voltage at given temp
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$analysis(analysis_string1<, analysis_string2 <, ...>>)
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Returns true(1) if the current analysis phase matches one of the given analyses strings. The following are the examples of analyses strings: "dc", "tran", "ac", "pss", "noise", "pdisto", "qpss", "pac", "pnoise", "pxf", "sp", "tdr", "xf", "envlp", "psp", "qpsp", "qpac", "qpnoise", "qpxf", "static", "ic", and so on.
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Parameter Functions
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$pwr( x )
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Assignment of model power consumption. Adds the expression x to the pwr parameter of a module.
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Data Types
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integer
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Discrete numerical type.
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real
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Continuous numerical type.
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Data Qualifiers
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parameter
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Indicates that a variable is a parameter and so may be given a different value when the module is instantiated, and that it may not be assigned a different value inside the module.
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Structural Statements
Structural statements are used inside the module block but outside the analog block.
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module_or_primitive #(<.param1(expr1)<,...>>) inst_name (<node1 <, ..>> );
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Creates a new instance of module_or_primitive named inst_name.
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Environment Variables
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CDS_AHDLCMI_SHIPDB_COPY
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Set this environment variable to YES to use AHDL ship databases (ahdlShipDBs). When the environment variable is to YES, the software creates an ahdlShipDB for each Verilog-A file in the directory that contains the Verilog-A file, if the directory is writable. If the directory is not writable, the software does not create any ahdlShipDBs for the modules in the Verilog-A file (see CDS_AHDLCMI_SHIPDB_DIR).
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CDS_AHDLCMI_SHIPDB_DIR
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Specifies the path to a directory for ahdlShipDB. All Verilog-A files share this path. If the path specified by this variable is not writable, or the path does not exist, the software does not create any ahdlShipDB and generates a warning. For example, setenv CDS_AHDLCMI_SHIPDB_DIR /export/shared/objects.
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CDS_AHDL_COMPILEC_MAX_LOAD
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Set this environment variable to change the max_load value for parallel compilation of AHDL generated C code. When the system load average is above max_load, parallel compilation is turned off. For example, setenv CDS_AHDL_COMPILEC_MAX_LOAD 4.0.
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CDS_AHDL_DDT_SCALE
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Set this environment variable to scale the value of ddt to the specified range for better convergence. The default value is 1e-17.
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CDS_AHDL_FINISH_MODE
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Set this environment variable to 1 to cause the $finish function to stop the current analysis instead of stopping the whole simulation. The default value is 0.
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CDS_AHDL_IDT_SCALE
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Set this environment variable to scale the value of idt to the specified range for better convergence. The default value is 1.
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CDS_AHDL_IGNORE_HIDDEN_STATE
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Set this environment variable to YES to process all hidden state variables as non-hidden state variables for all Verilog-A modules.
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CDS_AHDL_IGNORE_OPPOINT
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Set this environment variable to YES to ignore all operating point calculations. Set the environment variable to NO to disable optimization. The default value is YES for compact models and NO for normal models.
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CDS_AHDL_REUSE_LIB
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In +aps, ++aps, +xps and +ms modes, the software automatically searches the pre-run shared library and reuses it. Set this environment variable to NO to disable the automatic search and reuse of pre-run shared library.
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CDS_CMI_COMPLEVEL
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Set this environment variable to control GCC optimization level when compiling AHDL-generated C code flow. The environment value is from 0 to 3, which implies that GCC will use level O0 ~ O3 to compile AHDL C code. O3 is the default compilation level and gives better optimization.
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CDS_VLOGA_INCLUDE
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Set this environment variable to specify the directory that contains the file with the "include" directive. You can specify more than one directory by using comma(,), colon(:), or semicolon(;) as delimiters to separate the directories. For example, setenv CDS_VLOGA_INCLUDE "dir1;dir2" or setenv CDS_VLOGA_INCLUDE dir1:dir2.
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CDS_AHDL_LRM_COMPATIBILITY
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Set this environment variable to specify the version of LRM. The default value is 2.3. For example, setenv CDS_AHDL_LRM_COMPATIBILITY 2.4.
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CDS_AHDL_AUTOGDEV_SUPPORT
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Set this environment variable to NO to prevent a Verilog-A model from automatically adding the simulation parameter gdev at a non-linear branch when the kernel uses the gdev method. The default value is YES, which means that the Verilog-A model adds the simulation parameter gdev by default.
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CDS_AHDL_AUTOGMIN_INSERT
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Set this environment variable to YES to enable a Verilog-A model to add the simulation parameter gmin at a non-linear branch. The default value is NO.
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