vhdlKeepCaseAsNC
vhdlKeepCaseAsNC = { t | nil }
Description
By default, names of VHDL identifiers (such as entity, port and architecture names) are lower cased when the vmsUpdateCellViews function is run.
When set to t, preserves the case of entity and port names when the vmsUpdateCellViews function is run. For escaped names, the case is preserved for all identifiers. You must also add the following entry in the hdl.var file:
define ncvhdlopts -keepcase4use5x
When set to nil, names of VHDL identifiers are lowercased.
- Architecture names are always lowercased.
-
Cadence recommends that you do not use the following environment variable to preserve the case of entity and port names:
CDS_ALT_NMP=match
For example, consider the following VHDL entity:
entity myEntity is
port(
VIn : In bit
Vout : out bit
);
When the vmsUpdateCellViews function is run, by default, the symbol view contains lower cased port names vin and vout. The entity name is also converted to lowercase and saved as myentity.
In this case, the original VHDL text view is not modified. Instead, a new VHDL entity view is created.
Example
vhdlKeepCaseAsNC = t
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