vmsCreateMissingMasters

vmsCreateMissingMasters = { t | nil }

Description

When set to t, the environment creates skeleton Verilog-AMS descriptions and symbols for undefined modules by using explicit port names (when the instances are connected explicitly) or by using connecting module port names (when the instances are connected implicitly). If these approaches fail, the environment uses dummy names for ports. The direction assigned to each port is based on the direction of the connecting net, if a direction is set.

The default value is nil, which indicates that the environment does not create skeleton descriptions or symbols for undefined modules.

Example

vmsCreateMissingMasters = t