vmsPortProcessing

vmsPortProcessing = "Analog" | "Digital" | "Mixed"

Description

Determines how port concatenations are handled when the environment generates a Verilog-AMS text view from another cellview.

Possible values are:

• Analog: Port concatenations remain as concatenations in the generated cellviews.
• Digital: Port concatenations remain as concatenations in the generated cellviews. This is the default value for verilog text views when schHdlUseVamsForVerilog is set to t.
• Mixed: Port concatenations in generated cellviews are translated to the format expected by the AMS netlister. This is the default value for verilog-ams text views. This is the default value for verilog text views when schHdlUseVamsForVerilog is set to nil.

Example

You have a symbol with two terminals named a<2:3>,b,c<1> and c<2:3>,b. If vmsPortProcessing is set to Analog or Digital and the terminals are of the inout type, the AMS Designer environment creates the following skeletal text module from the symbol.

module <name> ( {a[2:3], b, c[1]}, {c[2:3], b} );
    inout  [1:3] c;
    inout  b;
    inout  [2:3] a;
endmodule

If vmsPortProcessing is set to Mixed, the AMS Designer environment creates the following skeletal module, which is in the format expected by the AMS netlister.

module <name> ( a, b, c )
    inout  [1:3] c;
    inout  b;
    inout  [2:3] a;
endmodule