19
File Formats
This section contains explanation of different files used in Voltus-Fi-XL.
Activity File
A file that contains the activity factor on any node of the circuit. This file is used for average current analysis. In the GUI, you can specify the activity file in the Advanced tab of the Setup and Run Current Analysis form.
Command: run_static_simulation -activity_file file_name
The activity file has the following format:
file :rows EOF //a file consists of rows of information
rows :ε //an empty line
|comment //a comment line
|line //a specification line
comment :^[\t]*\*.* EOL //a line starting with * is a comment
line :name FA_value //a node with transitional frequency
- Name can be the name of any node in the circuit.
-
FA_value specifies the default nodal activity to be used. It is given as an activity factor. A value of
0.20would be20%of the default frequency.
Example: This is a sample fa_file for node activities. The column on the left shows the node names and the column on the right shows the activity.
out01 2
out02 3
out03 4
Clock File
A file that contains information about the clock nodes, subcircuit definitions, and subcircuit instance names and their frequencies. This file is used only for average static current analysis. In the GUI, you can specify the average power file in the Advanced tab of the Setup and Run Current Analysis form.
Command: run_static_simulation -clock_file clock_file_name
file: rows EOF //a file consists of rows
rows: ε //an empty line
| comment //a comment
| line //a specification line
comment:^[\t]*\*.+EOL //a line starting with a *
line :CLK name freq_value //a clock node specification
|INST name freq_value //a subcircuit instance specification
|INST name freq_value activity //a subcircuit instance with activity
|CELL name freq_value //a subcircuit definition specification
|CELL name freq_value activity //a subcircuit definition with activity
CLK, INST, and CELL are keywords.
-
If you use the
CLKkeyword, the node name is treated as the root of a clock running at the given frequency. -
If you use the
INSTkeyword, all input and output nodes—that is, node names on the instance card—are set to toggle at the specified frequency. . -
If you use the
CELLkeyword, all instances of the cell are processed instead of a single instance.
CLK has precedence over INST, and INST overrides CELL information to resolve redundant specifications.
Example: The following example specifies the CLK keyword in column 1, clock name in column 2, and the frequency value in column 3.
Value Change Dump File
A file that contains information about the number of transitions for each net. This file is used only for average static current analysis. In the GUI, you can specify the VCD file in the Advanced tab of the Setup and Run Current Analysis form.
Command: run_static_simulation -vcd vcd_file_name
Within the VCD file, these VCD values have the following meanings during driving:
-
0
Forces the associated node to logic low. -
1
Forces the associated node to logic high. -
X
Forces the associated node to logic unknown. -
Z
Releases the associated node.
The following extensions of the VCD format are supported. You can use these command extensions in the comment section of a VCD file to specify node characteristics.
Use these extensions to specify properties such as input voltages and rise and fall times of nodes listed in the VCD file.
-
*scope
Sets the scope of thenodesetcommand by using thescopecommand. Scope_string is prepended to the nodes listed in thenodesetcommand. The syntax is as follows:*scope scope_string *end
-
*nodeset
Groups nodes in the VCD file into node sets. You can then set properties of the nodes in the node set by using theparamscommand on the node set. The syntax is as follows:
*nodeset set_number [node_name]+ *end -
*params
Assigns parameters to sets of nodes by using theparamscommand. The syntax is as follows:*params set_number <vin0=voltage> <vin1=voltage> <vinx=voltage><tir=time><tif=time> *end
Following is a sample VCD file named vcd.
$date
Thurs Mar 07 15:09:59 2013
$end
$version
Cadence 1.0
$end
$timescale
1ns
$end
$scope module TOP $end
$var wire 1 ! A[7] $end
$var wire 1 " A[6] $end
$var wire 1 # A[5] $end
$var wire 1 $ A[4] $end
$var wire 4 % A[3:0] $end
$upscope $end
$comment
*scope TOP *end
*nodeset 1 A[7:0] *end
*params 1 vin0=0v vin1=5v vinx=2.5v tir=1ns tif=1ns *end
$end
$enddefinitions $end
#0
1!
1"
1#
1$
b1111 %
#50
0!
0"
0#
0$
b0000 %
#50
1$
b0001 %
#50
1#
0$
b0010 %
#50
1$
b0011 %
#50
1"
0#
0$
b0100 %
Power File
A file that contains the average power for specific sub circuits. This file is used only for average static current analysis. In the GUI, you can specify the average power file in the Advanced tab of the Setup and Run Current Analysis form.
Command: run_static_simulation -power_file power_file_name
The average power file has the format shown in the following example:
CELL C_MUX2_TG 2.0e-4
Xxev | xeu | xem | wpy | sdh 1.0e-3
The CELL keyword specifies that the name following it is a subcircuit definition and that all instances of the cell dissipate the same average power. If the file does not contain the CELL keyword, the name is an instance of a subcircuit dissipating the specified average power.
ICT File
The ICT file specifies the EM reliability rules for EM analysis. This is a text-based file, which means you can use any text editor to enter information in this file.
Following is a sample ICT file.
process "abcd" {
background_dielectric_constant 1
temp_reference 25
em_tref 110
em_output_wlt drawn
em_variables w delta_T
em_conductor_unit mA/um
em_via_area_unit mA
em_via_unit mA
em_dc_rms_metal_line_num 3
em_ac_rms_metal_line_num 3
simulation {
manual_simulation_points {
metal_layer "mt1" {
simulation_widths 0.3 0.6 1.5 3
simulation_spacings 0.3 0.6 1.5 3
}
metal_layer "mt2" {
simulation_widths 0.3 0.6 1.5 3
simulation_spacings 0.3 0.6 1.5 3
}
}
manual_simulation_combinations {
combination_layers "mt1" "mt2"
separation_values 0 1 2 3
}
}
}
conductor "mt1" {
min_spacing 0.3
min_width 0.3
height 1.05
thickness 0.53
resistivity 0.1
gate_forming_layer false
thermal_conductivity 0.39
em_model {
em_jmax_dc_rms_metal_line_factor 1 1.5 2 1.5 3 1.32 4 1.32 5 1.05 6 1.05 7 1.05 8 1.05 9 1
em_jmax_ac_rms_metal_line_factor 1 1.5 2 1.5 3 1.32 4 1.32 5 1.05 6 1.05 7 1.05 8 1.05 9 1
em_jmax_dc_avg EQU w*1.0 jmax_factor 50 1.1 110 1.0 125 0.92 L > 5
em_jmax_dc_avg EQU w*3.0 jmax_factor 50 1.1 110 1.0 125 0.92 L <= 5
em_jmax_dc_peak EQU w*1.5 jmax_factor 50 1.1 110 1.0 125 0.92 L > 5
em_jmax_dc_peak EQU w*3.5 jmax_factor 50 1.1 110 1.0 125 0.92 L <= 5
em_jmax_dc_rms EQU 1.5 * sqrt(2*delta_T)
em_jmax_ac_rms EQU 1.5 * sqrt(2*delta_T)
}
}
conductor "mt2" {
min_spacing 0.3
min_width 0.3
height 2.38
thickness 0.53
resistivity 0.1
gate_forming_layer false
thermal_conductivity 0.39
em_model {
em_jmax_dc_rms_metal_line_factor 1 1.5 2 1.5 3 1.32 4 1.32 5 1.05 6 1.05 7 1.05 8 1.05 9 1
em_jmax_ac_rms_metal_line_factor 1 1.5 2 1.5 3 1.32 4 1.32 5 1.05 6 1.05 7 1.05 8 1.05 9 1
em_jmax_dc_avg EQU 2.0*w*1.0 jmax_factor 50 1.1 110 1.0 125 0.92 L > 5
em_jmax_dc_avg EQU 2.0*w*3.0 jmax_factor 50 1.1 110 1.0 125 0.92 L <= 5
em_jmax_dc_peak EQU 2.0*w*1.5 jmax_factor 50 1.1 110 1.0 125 0.92 L > 5
em_jmax_dc_peak EQU 2.0*w*3.5 jmax_factor 50 1.1 110 1.0 125 0.92 L <= 5
em_jmax_dc_rms EQU 1.5 * sqrt(2*delta_T)
em_jmax_ac_rms EQU 1.5 * sqrt(2*delta_T)
}
}
via "Via1" {
top_layer "mt2"
bottom_layer "mt1"
contact_resistance 1.1
thermal_conductivity 0.39
em_model {
em_jmax_dc_rms_metal_line_factor 1 1.5 2 1.5 3 1.32 4 1.32 5 1.05 6 1.05 7 1.05 8 1.05 9 1
em_jmax_ac_rms_metal_line_factor 1 1.5 2 1.5 3 1.32 4 1.32 5 1.05 6 1.05 7 1.05 8 1.05 9 1
em_vcwidth 0.12
em_jmax_dc_avg 1.0 jmax_factor 50 1.1 110 1.0 125 0.97
em_jmax_dc_peak 1.5 jmax_factor 50 1.1 110 1.0 125 0.97
em_jmax_dc_rms EQU 1.5 * sqrt(2*delta_T)
em_jmax_ac_rms EQU 1.5 * sqrt(2*delta_T)
}
EM Only ICT File
The EM only ICT file provides the process and the EM model information for EM analysis. This is a text-based file, which means you can use any text editor to enter information in this file.
Following is a sample EM only ICT file.
process "gpdk090" {
background_dielectric_constant 1.000000
temp_reference 25
layout_scale 0.9
#! use_silicon_density true
em_tref 110
em_output_wlt drawn
em_variables w delta_T
em_conductor_unit mA
em_via_area_unit mA
em_via_unit mA
em_peak_with_duty_ratio explicit
}
conductor "mt1" {
em_model {
em_jmax_dc_avg EQU 100 * 1* ( w - 0.008 ) jmax_factor 100 2.077 105 1.434 110 1.000 115 0.704 120 0.500 125 0.358 L > 9 W < 0.45
em_jmax_dc_avg EQU 150 * 1.227 * ( w - 0.008 ) jmax_factor 100 2.077 105 1.434 110 1.000 115 0.704 120 0.500 125 0.358 L <= 9 L > 4.5 W < 0.45
em_jmax_dc_avg EQU 200 * 1.227 * ( w - 0.008 ) jmax_factor 100 2.077 105 1.434 110 1.000 115 0.704 120 0.500 125 0.358 L > 9 W >= 0.45
em_jmax_dc_avg EQU 200 * 1.227 * ( w - 0.008 ) jmax_factor 100 2.077 105 1.434 110 1.000 115 0.704 120 0.500 125 0.358 L <= 9 L > 4.5 W >= 0.45
em_jmax_dc_avg EQU 400 * 1.227 * ( w - 0.008 ) jmax_factor 100 2.077 105 1.434 110 1.000 115 0.704 120 0.500 125 0.358 L <= 4.5
em_jmax_dc_peak EQU 25.0 * ( w - 0.008 )
em_jmax_ac_peak EQU 25.0 * ( w - 0.008 )
em_jmax_dc_rms EQU sqrt( 18.58 * delta_T * ( w - 0.008 )^2 * ( w - 0.008 + 0.246 ) / ( w - 0.008 + 0.0443 ) )
em_jmax_ac_rms EQU sqrt( 18.58 * delta_T * ( w - 0.008 )^2 * ( w - 0.008 + 0.246 ) / ( w - 0.008 + 0.0443 ) )
}
}
EM Data File
An EM data input file specifies the technology information, such as current density limits, and provides a mapping between the layers for highlighting.
Following is a sample EM data file.
(
; this file is case sensitive
routingLayers = ("Poly" "Metal1" "Metal2" "Metal3" "Metal4" "Metal5" "Metal6")
viaLayers = ("Cont" "Nimp" "Pimp" "Via1" "Via2" "Via3" "Via4" "Via5")
viaWidthList = (("Nimp" 0.2) ("Pimp" 0.2) ("Cont" 0.2) ("Via1" 0.2)
("Via2" 0.2) ("Via3" 0.2) ("Via4" 0.2) ("Via4" 0.2))
xrefLayers = (
( "POLYcont" ("Cont" "Cont"))
( "NSDcont" ("Nimp" "Nimp"))
( "PSDcont" ("Pimp" "Pimp"))
( "poly" ("Poly" "Poly"))
( "mt1" ("Metal1" "Metal1"))
( "mt2" ("Metal2" "Metal2"))
( "mt3" ("Metal3" "Metal3"))
( "mt4" ("Metal4" "Metal4"))
( "mt5" ("Metal5" "Metal5"))
( "mt6" ("Metal6" "Metal6"))
( "Via2NoCapInd" ("Via2" "Via2"))
( "Via2" ("Via2" "Via2"))
)
avgCurrentDensSpecList = (
(nil layer "Poly" minW 0.0 maxW -1.0 minL 0 maxL 5 currentDensity ((1.0 , 110)))
(nil layer "Metal1" minW 0.0 maxW -1.0 currentDensity ((1.1 , 110)))
(nil layer "Metal2" minW 0.0 maxW -1.0 currentDensity ((1.2 , 110)))
(nil layer "Metal3" minW 0.0 maxW -1.0 currentDensity ((1.3 , 110)))
(nil layer "Metal4" minW 0.0 maxW -1.0 currentDensity ((1.4 , 110)))
(nil layer "Metal5" minW 0.0 maxW -1.0 currentDensity ((1.5 , 110)))
(nil layer "Metal6" minW 0.0 maxW -1.0 currentDensity ((1.6 , 110)))
(nil layer "Cont" minW 0.0 maxW -1.0 res 1.0 currentDensity ((2.0 , 110)))
(nil layer "Nimp" minW 0.0 maxW -1.0 res 1.1 currentDensity ((2.1 , 110)))
(nil layer "Pimp" minW 0.0 maxW -1.0 res 1.2 currentDensity ((2.2 , 110)))
(nil layer "Via1" minW 0.0 maxW -1.0 res 1.3 currentDensity ((2.3 , 110)))
(nil layer "Via2" minW 0.0 maxW -1.0 res 1.4 currentDensity ((2.4 , 110)))
(nil layer "Via3" minW 0.0 maxW -1.0 res 1.5 currentDensity ((2.5 , 110)))
(nil layer "Via4" minW 0.0 maxW -1.0 res 1.6 currentDensity ((2.6 , 110)))
(nil layer "Via5" minW 0.0 maxW -1.0 res 1.7 currentDensity ((2.7 , 110)))
)
peakCurrentDensSpecList = (
(nil layer "Poly" minW 0.0 maxW -1.0 currentDensity ((1.1 , 110)))
(nil layer "Metal1" minW 0.0 maxW -1.0 currentDensity ((1.2 , 110)))
(nil layer "Metal2" minW 0.0 maxW -1.0 currentDensity ((1.3 , 110)))
(nil layer "Metal3" minW 0.0 maxW -1.0 currentDensity ((1.4 , 110)))
(nil layer "Metal4" minW 0.0 maxW -1.0 currentDensity ((1.5 , 110)))
(nil layer "Metal5" minW 0.0 maxW -1.0 currentDensity ((1.6 , 110)))
(nil layer "Metal6" minW 0.0 maxW -1.0 currentDensity ((1.7 , 110)))
(nil layer "Cont" minW 0.0 maxW -1.0 res 1.0 currentDensity ((2.1 , 110)))
(nil layer "Nimp" minW 0.0 maxW -1.0 res 1.1 currentDensity ((2.2 , 110)))
(nil layer "Pimp" minW 0.0 maxW -1.0 res 1.2 currentDensity ((2.3 , 110)))
(nil layer "Via1" minW 0.0 maxW -1.0 res 1.3 currentDensity ((2.4 , 110)))
(nil layer "Via2" minW 0.0 maxW -1.0 res 1.4 currentDensity ((2.5 , 110)))
(nil layer "Via3" minW 0.0 maxW -1.0 res 1.5 currentDensity ((2.6 , 110)))
(nil layer "Via4" minW 0.0 maxW -1.0 res 1.6 currentDensity ((2.7 , 110)))
(nil layer "Via5" minW 0.0 maxW -1.0 res 1.7 currentDensity ((2.8 , 110)))
)
Layer Map File
The layer map file or map file provides the mapping between the layer names in the simulation database to those specified in the technology files (qrcTechFile and ICT file) for the EM analysis flow. It maps the layer names in the xDSPF file to the ICT layer names. It is needed under either of the following circumstances:
- When a 3rd party xDSPF file with different layer names is used, or
-
When Quantus package uses the
layerSetupFile, which includes the"model"keywords to define parasitic resistor model names. For example,pro_layer=M1 ext_layer=MET1 model=metal1
In this case, the"metal1"to"M1"mapping needs to be specified in the layer map file.
The sample command for the above in the.cdsinitfile will be specified as follows:envSetVal("spectre.envOpts" "emLayerMap" 'string "/your-path/layermapfile")
Sample filename: contactmapfile.txt
RCX keyword simulation DB layername ICT keyword technology file layername
RCX specifies the keyword for the simulation database.
simulation DB layername specifies the layer names in the simulation database that are to be mapped to the technology file layer names.
ICT specifies the keyword for the technology file.
technology file layername specifies the layer names in the technology file that map to those in the simulation database.
<RCX keyword> <simulation DB layername> <ICT keyword> <technology file layername>
RCX metal1 ICT mt1
RCX metal2 ICT mt2
RCX metal3 ICT mt3
RCX metal4 ICT mt4
RCX pl1co ICT poly
RCX VIA1 ICT via1
DFII Layer Map File
The APS/XPS-to-DFII layer map file provides the mapping between the layer names in the extractor-generated xDSPF file to the DFII layer names.
Multiple extraction layers can be mapped to the same DFII layer. This layer map file is also used for performing structural analysis.
Sample filename: df2layermap.txt
type extraction_layer_name dfII_layer_name
type specifies the type of layer; for example, metal, via, or poly.
extraction_layer_name specifies the name of the layer in the extractor-generated xDSPF file that is to be mapped to the DFII layer.
dfII_layer_name specifies the name of the DFII layer to which the extractor-generated layer name is being mapped.
#<type> <extraction_layer_name> <dfII_layer_name>
via via3 Via3
metal mt3 Metal3
via via2_out_capind Via2
metal mt2 Metal2
via via1 Via1
metal mt1 Metal1
via cont_ndiff Cont
via cont_pdiff Cont
Support for User-Specified Purpose
By default, Voltus-Fi reads only the “drawing” purpose for the layers specified in the DFII layer map file. However, you can specify additional purpose names in the file for highlighting their shapes. For example,
metal m1 M1 e1 e2
Where e1 and e2 are additional purpose names whose shapes are to be highlighted.
shParamFile
This file is the self-heating effect analysis parameter file, which is required for plotting the self-heating effect analysis plots.
self_heat_parameters {
K_SH_Scale = 1.23
beta_c1 = 0.0012
beta_c2 = 0.0023
beta_c3 = 0.0034
device_layers {
layer "OD" {
Rth = 1000
finger_effect = 2.0 * (1-exp(-0.3 * finger_num))
fin_effect = 1.0 - ( 0.018 * (10 - fin_num) )
}
layer "OD_2" {
Rth = 500
finger_effect = 2.0 * (1-exp(-0.4 * finger_num))
fin_effect = 1.0 - ( 0.019 * (30 - fin_num) )
}
}
conductor_layers {
layer "M1" {
alpha_connecting = 0.50
alpha_overlapping = 0.40
}
layer "M2" {
alpha_connecting = 0.45
alpha_overlapping = 0.35
}
}
Trigger File
The file format of the trigger file is:
CELL <cellname1>
MODE_NAME <mode1>
CONDITIONAL_INPUT <conditional input statement for cellname1>
CONDITIONAL_PIN <pin_name> (rise| fall | both)
SIM_START_TIME <time>
SIM_STOP_TIME <time>
END_MODE
"|" denotes boolean OR operation
The table below lists the contents of the trigger file and provides their descriptions.
CELL adc_sample
# MODE_NAME READ
MODE READ
CONDITIONAL_INPUT = ( WEN & !CEN )
CONDITIONAL_PIN CLK { RISE }
SIM_START_TIME 35ns
SIM_END_TIME 50ns
END_MODE
MODE WRITE
CONDITIONAL_INPUT = ( !WEN & !CEN )
CONDITIONAL_PIN CLK { RISE }
SIM_START_TIME 15ns
SIM_END_TIME 30ns
END_MODE
MODE STBY
CONDITIONAL_INPUT = ( CEN )
CONDITIONAL_PIN CLK { RISE }
SIM_START_TIME 80ns
SIM_END_TIME 120ns
END_MODE
END
"!" denotes low state of the signal
"&" denotes boolean AND operation
LEF layer Map File
A layer mapping file is required for the Rail Analysis library generation flow. The LEF layer map file contains the mapping information to map the layer names in the LEF file to the layer names in the technology file.
In the GUI, you can specify this file in the Create Power Grid Views form.
Sample filename: lefdef.layermap
Command: create_pgv -lef_layer_map lef_layer_map_file_name
type technology_layer_name lefdef lef_layer_name
type specifies the type of library layer, for example, metal or via.
technology_layer_name specifies the name of the library layer to map to the LEF layer.
lefdef specifies the keyword for the LEF layer mapping.
lef_layer_name specifies the name of the LEF layer to map to the library layer.
type technology_layer_name lefdef M1
metal METAL_1 lefdef M1
via VIA_1 lefdef VIA1
metal METAL_2 lefdef M2
via VIA_2 lefdef VIA2
where “type” can be poly/via/metal/diff.
PGDB layer Map File
A layer mapping file is required for the Rail Analysis library generation flow. The PGDB layer map file contains the mapping information to map the xDSPF layer names that are written in the simulation database to the layer names in the technology file.
In the GUI, you can specify this file in the Create Power Grid Views form.
Command: create_pgv pgdb_layer_map pgdb_layermap_file_name Format:
type technology_layer_name pgdb xDSPF_layer_name
type specifies the type of library layer. It can be poly/via/metal/diff.
technology_layer_name specifies the name of the library layer to map to the xDSPF layer name.
pgdb specifies the keyword for the xDSPF layer mapping.
xDSPF_layer_name specifies the xDSPF layer name.
type technology_layer_name pgdb pgdb_layer_name
# ---- --------------------- ---- ---------------Note:
poly POLYCIDE pgdb poly
via CONT pgdb pl1co
via CONT pgdb odCont1
via CONT pgdb odCont2
metal METAL_1 pgdb metal1
via VIA_1 pgdb VIA1
metal METAL_2 pgdb metal2
via VIA_2 pgdb VIA2
diff OD pgdb nwires
diff OD pgdb mwires
-
It is recommended to map the S/D diffusion layer to the original layer name instead of
mwiresin the PGDB layer map file. -
When generating PGVs from Voltus-Fi, some of the layers are not required for analysis, but must be preserved to maintain connectivity. Voltus-Fi supports mapping of these layers to a special layer "
connectivity" in the layer map file. An example is shown below.
type technology_layer_name pgdb xDSPF_layer_name
diff connectivity pgdb nwires
diff connectivity pgdb mwires
Common Command Language File
The common command language (CCL) file or the Quantus command file is used to specify the various commands and options that define the extraction run. This command file defines the various input files and libraries that make up the design, the output format, and the desired parasitics to extract from the design. The format and example of a CCL file generated in Voltus-Fi XL is provided below.
Lines in the CCL file are in the following general Tcl format:
where argument_list is a list of name-value pairs.
For more information about the Quantus command file or CCL format, see the “Quantus Command Files” chapter in the Quantus Extraction Users Manual.
An example of the Voltus-Fi-generated CCL file is below. The customized extract command file, myextract.txt, is also shown below:
The myextract.txt is as follows:
extract \ -selection "all" \ -type "rc_coupled"
The Voltus-Fi-generated CCL file used to extract xDSPF is as follows:
extract \ -selection "all" \ -type "rc_decoupled"
extraction_setup \ -analysis "em" \ -array_vias_spacing "0.35" \ -max_fracture_length infinite \ -max_fracture_length_unit "MICRONS" \ -max_fracture_via_count 1 \ -max_via_array_count_by_layer "Via1 1" "Via2 1" "Via3 1" "Via4 1" "Via5 4" "Via6 4" "Via7 4" "Via8 4" "Via9 4" "Via10 4" "Via11 4" \ -net_name_space "SCHEMATIC"
hierarchical_extract \ -split_feedthrough_pins "true"
filter_res \ -min_res 0.001 \ -remove_dangling_res false
filter_cap \ -exclude_floating_nets "true" \ -exclude_floating_nets_limit 50000
output_db \ -type dspf \ -subtype extended \ -add_explicit_vias true \ -busbit_delimiter "\[\]" \ -disable_instances false \ -hierarchy_delimiter "/" \ -include_cap_model "false" \ -include_res_model "false" \ -include_parasitic_cap_model "false" \ -include_parasitic_res_model "comment" \ -include_parasitic_res_length "true" \ -include_parasitic_res_width false \ -include_parasitic_res_width_drawn true \ -output_xy \ "CANONICAL_RES" \ "PARASITIC_RES" \ "GENERIC" \ -netlist_coupling_values "single" \ -add_bulk_terminal false \ -sub_node_char "#" \ -device_finger_delimiter "@" \ -include_parasitic_res_temp_coeff "true" \ -reduce_i_cards "true"
output_setup \ -directory_name "vfi_quantus101" \ -file_name "vfi_quantus101/testrun.dspf" \ -net_name_space "SCHEMATIC" \ -temporary_directory_name "vfi_temp" \ -compressed false
process_technology \ -technology_library_file "tech.lib" \ -technology_name "tech" \ -temperature 25.000000
input_db \ -type pegasus \ -directory_name "testdir" \ -hierarchy_delimiter "/" \ -run_name "testrun"
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