Product Documentation
Virtuoso SystemVerilog Netlister User Guide
Product Version IC23.1, August 2023

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Introduction to Virtuoso SystemVerilog Netlister

Digital system verification uses the SystemVerilog language extensively, and this has introduced the Digital-Mixed-Signal (DMS) use model. The DMS use model allows discrete models to represent analog circuits. SystemVerilog allows you to use user-defined type and resolution functions, which make the net obsolete as a scalar object.

These use-model changes require a netlister that supports modern constructs, imports data from a design database, and produces a simulator-compatible netlist. A netlister that has these capabilities can traverse the design hierarchy to build the complete structure of a netlist. In such cases, the hierarchy can be a schematic view and a text view, or only a text view.

Virtuoso® SystemVerilog Netlister is a utility that helps you generate netlists of digital SystemVerilog designs. This utility imports configuration views of digital designs for netlist generation, directly parses and accesses SystemVerilog and Verilog text models and creates LRM-compliant SystemVerilog configurations to generate compatible netlists.

This topic describes how to use the SystemVerilog Netlister to configure the environment for generating netlists of SystemVerilog designs. This topic is aimed at developers and designers of integrated circuits and assumes that you are familiar with:

Licensing Requirements

Virtuoso SystemVerilog Netlister requires the following licenses:

For information about licensing in the Virtuoso Studio design environment, see Virtuoso Software Licensing and Configuration Guide.

Related Topics

Benefits of SystemVerilog Netlister

Benefits of SystemVerilog Netlister over NC Verilog Netlister

Launching SystemVerilog Netlister

SystemVerilog Netlister Batch Mode

Migrating SystemVerilog Integration Designs to SystemVerilog Designs


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