hnlGetSimulator

Returns SystemVerilog Netlister for SystemVerilog Netlister.

hnlUserShortCVList

Allows specifying a shorting list that contains devices that need to be shorted.

Example: hnlUserShortCVList=list(list(<libName> <cellName>))

simVerilogEnableEscapeNameMapping

Includes escaped names in the netlist. It also allows you to escape names that are reserved keywords in SystemVerilog.

Default value is t.

Example: If you have a module "assign" in your design, and you set simVerilogEnableEscapeNameMapping to t, it is mapped to "\assign" in the netlist.

simSVPortPropertyList

When enabled, allows specifying the dataType and portKind properties on a symbol cell. For example:

simSVPortPropertyList = '(  ("analogLib" "res" "symbol" "PLUS real var" "MINUS wrealdriver nil")  )

Here,

• "analogLib" indicates the library name
• "res" indicates the cell name
• "symbol" indicates the view name
• "PLUS real var" indicates that datatype is set to real, and portKind is set to var on port PLUS;
• "MINUS wrealdriver nil" indicates that only the datatype property is set to wrealdriver on port MINUS, leaving the portKind property blank.

vlogExpandIteratedInst

When set to nil, allows instances in the array in the following format:

"I_iter[0:2]"

When set to t, allows splitting iterated instances in the following format:

I_iter_1 …

I_iter_2 …

I_iter_3 …

hnlVerilogDumpIncludeFilesInNetlist

When set to t, copies the content of an included HDL file directly to the netlist, instead of inserting an `include statement.

The contents of the text cellviews in the design hierarchy are copied to the netlist. Any file specified in the Pre-Module Include File or In-Module Include File option of the SystemVerilog Netlister Options form is also copied to the netlist.

This variable works only in single netlist file mode. It does not support recursive inclusion of text files. Consider that fileA.sv includes fileB.sv. If you copy the contents of fileA.sv in the netlist using this variable, the contents of fileB.sv will not be copied in the netlist.

Default: nil

simVerilogGenerateSingleNetlistFile

A flag to generate a single Verilog netlist containing multiple modules instead of one netlist per module. By default, this flag is set to nil. If set to t, the netlister generates a single Verilog netlist file in the current simulation run directory with the name netlist.

hnlUserStopCVList

List of user specified cellviews, which are treated as stop views while netlisting a design. You can specify this list in the .simrc file. Although instances of such a cellview appear in a netlist, the cellview module is not printed in the netlist.

In the example below, all the cellviews in the libN library will be treated as stop views. However, in the lib1 library, only the cell1, cell2, and cell3 cellviews will be treated as stop views.

hnlUserStopCVList = list

( 

 ;;; all cells from this library
 "libN" 
;;; cell1, cell2 and cell3 from lib1
    list("lib1" "cell1" "cell2" "cell3"s)

)

vlogifDeclareGlobalNetLocal

A flag to declare global signals locally. When you disable this flag, the netlister uses the default signals (Global Power Nets and Global Grounds Nets). If the vlogifDeclareGlobalNetLocal flag is set to nil, global signals are declared in the cds_globals module.