Probing a Hierarchical Design

To probe a hierarchical design,

1. Open a hierarchical design in Layout XL.
   In the example below, this is Cellview Pair #1.
   
   
2. From the layout window menu bar, choose Connectivity – XL Probe.
3. Choose the instance to probe; for example, CV1, which is represented in the layout as pair of transistors (a flat representation).
4. Choose Edit – Hierarchy – Edit in Place.
   The schematic view of the inverter opens (CV3 in the diagram below).
   
   
   If you probe one of the transistors in this schematic, the corresponding transistor in the layout in the level above is highlighted (CV2 in the diagram).
5. In the inverter schematic (CV3), select one of the two NMOS instances.
6. In the schematic window, choose Launch – Layout XL to open the layout view for the inverter in Layout XL. This is CV4 in the diagram above.
   This creates another cellview pair, Cellview Pair #2.
7. To descend into the schematic of the inverter, select one of the NMOS instances and from the schematic window choose Edit – Hierarchy – Edit in Place.
   
   
   The schematic of the NMOS opens, CV5 in the diagram.
   If you probe the transistor in this schematic, the corresponding transistor in the layout in the level above is highlighted (CV4 in the diagram).
8. In the schematic window, choose Launch – Layout XL to open the layout of the transistor (CV6 in the diagram) in Layout XL.
   This creates another cellview pair, Cellview Pair #3. You can probe from NMOS: Schematic back to Top: Layout, Inv: Layout, and NMOS: Layout.

Related Topics

XL Probe Form

Design Probing

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