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Technology File Requirements for Layout XL

Virtuoso® Layout Suite XL layout editor (Layout XL) is a connectivity-based editing tool that automates each stage of the design flow, from component generation through automatic and interactive routing.
When used as part of an automated custom physical design methodology, Layout XL lets you generate a custom layout from a schematic and edit existing layouts that have defined connectivity. It continuously monitors connections of components in the layout and compares them with connections in the schematic. You can use Layout XL to view incomplete nets, shorts, invalid connections, and overlaps to help you wire your design.
This documentation is aimed at developers and designers of integrated circuits and assumes that you are familiar with:
- The Virtuoso Studio design environment and application infrastructure mechanisms supporting consistent operations between all Cadence tools.
- The applications for designing and developing integrated circuits in the Virtuoso Studio design environment, notably the Virtuoso Layout Suite L layout editor.
- Virtuoso technology data.
- Component description format (CDF), which lets you create and describe your own components for use with Layout XL.
The Layout XL and other Cadence® layout applications require technology-specific information about your design to be stored in a technology file for the design library.
The Virtuoso technology file comprises the following sections:
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functions( |
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A constraint group lets you specify the different sets of design constraints to be applied under different design circumstances or for different design objects. This allows the flexibility to experiment with more or less stringent process rules at different stages of the design process. You can group together any set of constraints into a constraint group, which can then be applied to any design associated with the technology library. |
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The two main types of technology devices used in Layout XL are vias and multipart paths.
Vias are required by the Create – Via and Create – Wire commands and by the Routing – Start Router command. Vias are defined by using
All the vias used in your design must be defined in the
For information about how via definitions are used to derive the connectivity rules for Layout XL, see Connectivity Rules.
Multipart path templates are defined in the |
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Physical rules are specified in the
The minimum requirement for Layout XL is the |
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constraintGroups( |
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The connectivity stack is a representation of the extractable layers and the associated electrical connections used by the Layout XL connectivity extractor. |
Related Topics
Virtuoso Technology Data ASCII Files Reference
Virtuoso Technology Data Constraint Reference
Virtuoso Technology Data SKILL Reference
Virtuoso Layout Suite SKILL Reference
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