Product Documentation
Virtuoso Abstract Generator User Guide
Product Version IC23.1, November 2023

Pin Names

You can specify the pin names in the Power pin names, Ground pin names, Clock pin names, Analog pin names, and Output pin names fields of the Running step Pins form. Abstract Generator identifies the respective pin names based on the label strings in the abstract. You can specify a list of possible names for the pins in the form of regular expressions, each separated by a space, as shown in the figure below.

By default, the Clock pin names, Analog pin names, and Output pin names fields are empty.

When Abstract Generator encounters a label that matches one of the regular expressions, it sets properties as given in the table below. In addition, Abstract Generator adds attributes for the pin in question to the LEF definition.

Pin Terminal Direction Terminal Type Attribute Added for LEF PIN in the LEF File

Power pin

inputOutput

power

USE POWER

Ground pin

inputOutput

ground

USE GROUND

Clock pin

input

clock

USE CLOCK

Analog pin

input

analog

USE ANALOG

Output pin

output

signal

USE OUTPUT

If there is a logical view present for the cell being processed, Abstract Generator checks whether a given terminal has a matching terminal in the logical view. If it does, the terminal direction is adopted from the terminal in the logical view. Otherwise, Abstract Generator uses the value specified in the Output pin names field to determine the output pins.

Related Topics

Specifying Pin Mappings for Abstract Generation

Regular Expressions for Creating Pin Names

Text Labels-to-Pins Mapping

Troubleshoot Pin Issues


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