A
ADE
Abbreviation for Analog Design Environment.The Cadence® Virtuoso® Analog Design Environment is the analog design and simulation environment for the Virtuoso custom design platform. It has became an industry's standard environment for simulating and analyzing full-custom, analog, and RF IC designs, and it is the task-based tool within the Virtuoso Specification-driven Environment.
AICM
Abbreviation for Automatically-inserted Connect Module.
access function
The method by which flows and potentials are accessed on nets, ports, and branches.
analog procedural block
A procedural sequence of statements that defines the behavioral description of a continuous time simulation.
B
BSIM
Abbreviation for Berkeley Short-channel IGFET Model.BSIM is a physics-based, accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley.
branch
A path between two nodes. Each branch has two associated quantities, a potential and a flow, with a reference direction for each.
C
CM
Abbreviation for connect module.A module inserted automatically or manually by using the connect statement, which contains the code required to translate and propagate signals between nets that have different discipline domains and that are connected through a port. Connect modules are also known as interface elements.
CMI
Abbreviation for Compile Module Interface.A Cadence API used to include model primitives in the C and C++ languages. CMI is shipped with the SPECTRE release. The CMI models can be used in Spectre, APS, UltraSim, XPS, and AMS-D simulators.
circuit topology
The interconnection of all the circuit elements with given parameters and port bindings.
collapsible and non-collapsible port connection
A port connection is collapsible if the upper and lower connections are nets. For connections of selects of packed or unpacked net arrays, the selects must have constant indices to be collapsible. It is important to note that, amongst other things, the presence of variables or constant expressions on either side of the connections makes the port connections non-collapsible.
D
DSPF
Abbreviation for Detailed Standard Parasitic Format.A file format to represent parasitic data.
DUT
Abbreviation for Design Under Test.Typically DUT refers to the portion of the simulation that is synthesized. The other portion of the simulation could be referred to as the test bench.
digital island
The set of drivers and receivers interconnected by a purely digital net.
discipline resolution
The process of assigning a domain and discipline to nets whose domain and discipline are otherwise unknown (or whose discipline is wire).
driver
A primitive device or behavioral construct that affects the digital value of a signal.
driver-receiver segregation
The conceptual severing of connections between drivers and receivers that occurs in mixed nets. When driver-receiver segregation occurs, digital signals propagate only through connect modules inserted between the drivers and receivers.
E
E2R
Abbreviation for Electrical-to-Real.An automatically-inserted connect module that connects a Verilog-AMS electrical object and a SystemVerilog Real object (wreal), and converts a signal with electrical discipline to logic real value.
G
GUI
Abbreviation for Graphical User Interface.
H
HDL
Abbreviation for Hardware Description Language.HDL is any language from a class of computer, specification, or modeling languages used for formal description and design of electronic circuits and digital logic. It can describe a circuit's operation, design and organization, and tests to verify its operation through simulation.
HED
Abbreviation for Hierarchy Editor.The Cadence hierarchy editor (HED) is used in the Cadence® Virtuoso flow to define the design partitioning during analog and mixed-signal simulation. The defined design partitioning is stored in a configuration file.
I
IE
Abbreviation for Interface Element.Also known as connect modules, interface elements work as analog-to-digital (A2D) and digital-to-analog (D2A) converters during mixed-signal simulation. IEs operate the electrical-to-logic and logic-to-electrical conversions. The Spectre® AMS Designer Simulator allows automatic insertion of IEs during elaboration.
M
mixed bus
A bus comprising at least one net from the analog domain and at least one net from the digital domain.
MOSFET
Abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor.MOSFET is a transistor used for amplifying or switching electronic signals. In MOSFET, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type and is accordingly called an nMOSFET or a pMOSFET (also commonly known as nMOS and pMOS).
MSDC
Abbreviation for Mixed-Signal DC.
mtline
Abbreviation for multi-conduction transmission line.Characterized by constant RLGC matrices or frequency-dependent RLGC data, an mtline can contain as many conductors as described in the input. However, there must be at least two conductors, with one conductor used as a reference to define terminal voltages. The reference conductor can be ground. The order of the conductors is the same as the order of the data in the input. The mtline model is included in Spectre, APS, UltraSim, XPS and AMS-D simulators.
MTS
Abbreviation for Multi-technology Simulation.Technology to enable the simulation of a system that consists of IC blocks to be manufactured with different processes.
N
NCF
Abbreviation for Netlist Compiled Function.The Spectre circuit simulator allows a netlist expression to call functions that are loaded from a Dynamic Link Library (DLL). By creating functions in C or C++, for example, it takes advantage of the features of these languages and overcomes the restrictions of the netlist user-defined function.
xmelab
Native code elaborator. The elaborator gathers various portions of a design and creates a snapshot that can be simulated (with xmsim). See Elaborator Options.
xmsim
Native code simulator. See Simulator Options.
xmvhdl
Native code VHDL compiler. See Introduction to the Xcelium Executables.
xmvlog
Native code Verilog compiler. See Introduction to the Xcelium Executables.
O
OMI
Abbreviation for Open Model Interface.An IEEE 1499 standard, which ensures open exchange of HDL-based IP. It is a language-neutral interface between models and simulation tools.
ordinary module
Any module other than a connect module.
OOMR
Abbreviation for Out-of-module reference.A direct reference from one Verilog module to another module that does not pass through any ports.
P
.pak
The NC Simulator stores output data from xrun, xmvlog, xmvhdl, and xmelab in one or more binary object files with the extension .pak , in the library in which the files are compiled.
PLI
Abbreviation for Programming Language Interface.A procedural interface that allows C/C++ functions to access the internal data structures of a SystemVerilog simulation. PLI includes SystemVerilog/Verification Procedural Interface (VPI) and VHDL Procedural Interface (VHPI).
PPE
Abbreviation for Post-processing Environment.Refers to the environment where simulation has finished and the results are being analyzed typically with a waveform viewer, as opposed to "live-simulation," where simulation is still running.
PSF
Abbreviation for Parameter Storage Format.When the AMS Designer simulator runs standalone, it writes the results of the AC analysis to a PSF file. By default, the software stores the PSF file in a directory called ascf.raw (where ascf is the name of the analog simulation control file).
PSL
Abbreviation for Property Specification Language.An IEEE 1850 standard for Property Specification Language.
PSO
Abbreviation for Power-shutoff.PSO, also called power gating, is one of the most effective power management techniques for reducing power. In PSO, selected functional blocks of the chip are individually powered down when they are not in use, to save leakage and dynamic power.
R
R2E
Abbreviation for Wreal-to-Electrical.A connect module, also known as an interface element, which converts digital logic values (0, 1, x, and z states) to real numbers.
receiver
A primitive device or behavioral construct that samples the digital value of a signal.
RNM
Abbreviation for Real Number Modeling or Real Number Models.Technique used to speed up simulation. As compared to SPICE and Fast SPICE simulators, RNM is more effective as it uses digital solvers (instead of analog solvers), and real ports and real variables in the behavioral code. During RNM simulation, the analog continuous blocks are represented with discrete real values computed in a digital solver. RNM simulations provide several magnitudes of simulation speed as compared to analog simulations. Though traditional analog verification flows provide accurate results, they are slower than RNM simulations. This is because analog solvers compute non-linear differential equations with matrixes, and such computations consume time and cost huge amount of CPU computations. Thus, unlike SPICE simulations, RNM displays high simulation speed gain, facilitates fast computation, and does not display convergence issues. RNM performance enables co-simulation of hardware and software in mixed-signal SoC verification.
RTSF
Abbreviation for Rain Tree Storage Format.Cadence proprietary format created by the Spectre, APS, UltraSim, and AMS-D simulators. RTSF is a PSF XL extension that provides improved viewing performance in the Virtuoso Visualization and Analysis XL tool. RTSF facilitates ultra fast viewing of data that contain a large number of time points.
S
SFE
Abbreviation for Simulation Front End.
SHM
Abbreviation for Simulation History Manager.A high-performance Cadence proprietary database for waveforms and related data used by NC-Sim, SimVision, ViVA, and other tools. It consists of a directory, typically with a ".shm" suffix, containing one or more SST2 database files.
singular interconnect
A singular interconnect is an interconnect which has no bounds declared. It represents a single atomic connection.
SPEF
Abbreviation for Standard Parasitic Exchange Format.An IEEE standard for representing parasitic data related to wires in a chip, in the ASCII format.
SST2
A Cadence proprietary database format used to store waveforms and related data in an SHM database directory. SST2 database files use the suffixes ".dsn," ".trn," and ".stc."
SV
Abbreviation for SystemVerilog.An IEEE P1800 standard for unified hardware design, specification, and verification language.
SVA
Abbreviation for SystemVerilog Assertion.
signal
A hierarchical collection of nets which, because of port connections, are contiguous.
T
topology
See circuit topology .
topology changes
Removal or introduction of nodes or using different devices in a design as a result of replacing subcircuit definitions or Verilog-A modules with respect to the original Spectre/SPICE files submitted to xmsim for simulation.
U
UDP
Abbreviation for User-defined Primitives.Allows designers to create objects during the modeling task. Multiple languages, such as Verilog and VHDL, support UDPs.
V
VCD
Abbreviation for Value Change Dump.A waveform format that SimVision can use; its format is ASCII-based and non-proprietary, allowing it to be used by many tools from different companies.
VPI
Abbreviation for SystemVerilog/Verification Procedural Interface.VPI provides a library of C-language functions and a mechanism for associating foreign language functions with SystemVerilog user-defined system task and system function names. SystemVerilog also has a DPI protocol for interacting with C code.
General Terms Related to Simulation
ABV
AXUM
Abbreviation for AMS Designer Xcelium Use Model. AXUM is a use model of AMS Designer dedicated for digital centric users, based on command-line simulation and SimVision debugging environment.
AVUM
Abbreviation for AMS Designer Virtuoso Use Model.A Cadence® Virtuoso® Analog Design Environment (ADE) based AMS Designer use model dedicated for analog- and mixed-centric users. The main difference between the AVUM and the AXUM flows is that AVUM is schematic based. It uses HED for design (analog/digital) partitioning. ADE provides netlisting, and the powerful and advanced simulation and post-processing cockpit.
AST
A VHDL syntax tree; an output data object type. NC and AMS-D simulators store such output data object type in the .pak file.
COD
Refers to code; is an output data object type. NC and AMS-D simulators store such output data object type in the .pak file.
DFII
Abbreviation for Design Framework II.Refers to the former Cadence Design Framework II, which has now become Virtuoso Design Environment in IC 6.1.
MDV
Abbreviation for Metric Driven Verification.Key methodology to silicon realization. MDV helps the design creators and integrators close the productivity gap (through improved approaches to design, verification, and implementation) and the profitability gap (by providing new capabilities for system optimization and IP creation, selection, and integration). MDV broadens the scope of the term "metrics" by including checks, assertions, and software- and time-based data points.
OA
Abbreviation for Open Access.A database format. OpenAccess data is supported by many industry-leading physical design tools, including the Cadence Virtuoso Custom Design Platform, as it helps eliminate tedious translation steps to save time and minimize misstep.
SAM
Abbreviation for Simulation Analog Master.An output data object type. NC and AMS-D simulators store such output data object type in the .pak file.
SIG
Overlay tables; an output data object type. NC and AMS-D simulators store such output data object type in the .pak file.
SSS
Abbreviation for Simulation Snapshot.An output data object type. NC and AMS-D simulators store such output data object type in the .pak file.
VHPI
Abbreviation for VHDL Procedural Interface.An interface that allows C-language programs access to VHDL design information and provides foreign language functions along with the ability to interact with a VHDL simulator through VHDL code.
VST
Abbreviation for Verilog Syntax Tree.An output data object type. NC and AMS-D simulators store such output data object type in the .pak file.