Platform Support
License Checkout Order for Mixed-Signal Designs
License Requirement Report
Feature-Specific License Checkout Order
Typographic and Syntax Conventions
Language Support
Versions of the Spectre AMS Designer Simulator
- Setting the Path Variable to Point to the 64-Bit Version
- Library Path Environment Variable
Running the AMS Designer Simulator
Single-step Approach to Running a Simulator
AMS Designer Flex Mode
Analog Solver Information
Analog Solvers Supported by AMS Designer Simulator
Advanced Analog Solver Features
Compatible Spectre Version Control File
The spectre_compatible_version.xml File Location
Switching Languages in the Analog Simulation Control File
- Using Spectre lookup Rules
Spectre Language Statements in the Analog Simulation Control File
Passing the Analog Simulation Control File to xrun
Passing the Analog Simulation Control File to xmsim
Spectre AMS Designer Analysis Support
Immediate Set Options (options)
AC Analysis Statement (ac)
Noise Analysis (noise)
Transient Analysis Statement (tran)
- Parameters
- Examples
Monte Carlo Analysis
EMIR Analysis in Spectre AMS Designer
Reliability Analysis in Spectre AMS Designer
Checklimit Analysis in Spectre AMS Designer
DC Analysis in Spectre AMS Designer
- fastdc Option
- dcopt Option
Sweep Analysis (sweep)
Stability Analysis (stb)
Transfer Function Analysis (xf)
Initial Conditions (ic) Statement
alter Statement
Alter Group (altergroup)
Device Checking and Violations Display
info Statement
- what
- where
- file
- extremes
- save
- title
- writedc
- Examples
save Statement
print Statement
Mixed-Signal DC Initialization
Comparing the Behavior of save Parameter Specified in an Analysis and the Global save Option
Circuit Checks for Spectre AMS Designer
Fault Analysis in Spectre AMS Designer
- Fault Simulation Use Model
- AMS Designer Spectre Fault Analysis Integration
nodeset Statement
nodeset Statement in Analog Simulation Control File
Spectre or APS Block-Based Transient Noise Analysis
State Information for Individual Analyses
Time-Saving Techniques for the Analog Solvers
- Adjusting Speed and Accuracy
- Saving Time by Selecting a Continuation Method
- Specifying Efficient Starting Points
amsd Block Statements and Syntax
portmap
Implicit and Explicit Port Mapping
Spice-to-Verilog Port Mapping
SPICE
config
Verilog 2001 Configuration File
ie
Dynamic Voltage Supply
Custom Connect Rules
Scope Assignments
Parameter Assignments
ce
connectmap
Integration between connectmap and ie Cards
Hierarchical Interface Element Optimization
- Hierarchical Optimization
- Interface Element Optimization between Dissimilar Nets
Discipline Resolution Optimization
Xcelium Mixed Signal: Co-Simulation Functionalities
Universal Connect Module (UCM)
UCM Compatibility with Legacy Connect Rules
UCM Use Model
Determining the Discipline of Analog Primitive Ports
Port Bindings
- Binding Ports by Order
Guidelines for Binding Ports by Name or Order
Parameter Binding
Analog Instances Inside Generate Statements
Subcircuits and Models
Compiled C Flow
- Incremental Compilation of C Code
- Disabling the Compile C Flow
Multi-Threading
Using mtline in a Schematic with AMS Simulator
Using mtline in a SPICE or Spectre Subcircuit or Model
Verilog-AMS Connect Modules for VHDL-SPICE Connection
Verilog-A Modules in SPICE Blocks
Verilog-AMS Vector Buses with SPICE Subcircuits
SPICE-on-Top
SPICE-in-the-Middle
Specifying DSPF and SPEF Stitching on Analog and Mixed-Signal Nets
SPICE Blocks in the Middle of VHDL Blocks
Using DSPF-in-the-Middle
-keepcase4use5x
Usage of Port Expressions when Connecting to Analog Blocks
SPICE Nets inside a Verilog Design
Reusing Mixed-Language Testbenches
- Using Command-Line Options to Manage Out-of-Module References to SPICE
- Using Compiler Directives to Manage Out-of-Module References to SPICE
- Using Bus Delimiters with Out-of-Module References to SPICE
Values Associated with an Analog Object
Strength-Based Interface Element (SIE)
PSL Assertions
Limitations of Using PSL Assertions
Reusing Testbenches and IP
Connecting VHDL Blocks to SPICE Blocks
Connections from VHDL and VHDL-AMS Blocks to Verilog and Verilog-AMS Blocks
Importing Verilog-AMS Modules into VHDL
Importing a Verilog-AMS Module
xmshell Command
Inherited Connections in VHDL-AMS
Mapping Verilog-AMS Disciplines to VHDL-AMS Natures
SPICE Built-In Primitives in VHDL-AMS and VHDL-Digital
String Type Literals and Generics in VHDL-AMS
VHDL-SPICE Conversion Element Optimization
CE Information in VHDL-SPICE
Basic wreal Features of the AMS Designer Simulator
Advanced wreal Features of the AMS Designer Simulator
Using the wreal Data Type
wreal Independent Variables in a $table_model
Verilog-AMS wreal and Analog Signal Connections
Resolving Disciplines for Verilog-AMS wreal Nets
VHDL Blocks with Real Signal Ports on a Schematic
wreal Nets at Mixed-Language Boundaries
Writing Bidirectional Model Behavior
Using wreal in Assertions
Selecting a wreal Resolution Function
- Order of Precedence for Determining the Resolution Function on a Net
- Rules to Determine the Resolved Resolution Function for Connected wreal Nets
Predefined wreal Resolution Functions
Verilog-AMS–Based RNM for Wreals
Writing RNMs Using Disciplineless Wreal Nets
Writing Portable Verilog-AMS Wreal Models for Use in SV
Wreal Concatenation Expressions
L2R and R2L Connect Modules
Port Connections through Real-to-Logic Connect Modules
Inherited Connections in R2L/L2R Connect Modules
Aliasing Nets to Hierarchical Nets in L2R/R2L Interface Elements
L2R/R2L Insertion in Multiple-Supply Designs
Electrical Supply in Real-to-Logic and Logic-to-Real Interface Elements
Virtuoso Visualization and Analysis in xrun and ADE Flows for Simulations with Real Number Models
Real Number Modeling Debug Options
wreal to VHDL Connections
xrun Command Syntax
xrun Command-Line Options for Mixed-Signal Designs
Examples Using xrun for AMS Simulation
Using xrun with Spectre and SPICE Input Files
Migrating to Single-Step XRUN Invocation
Mixed-Signal Design Debugging Reports
PSpice Netlist and Device Models
License Queuing
AHDL Linter
Turning on Spectre Parasitic Reduction
Turning on Spectre Multithreading for Device Evaluation
Turning off Spectre Multithreading
Simulation Diagnostics
Enabling AMS-APS Mode
AMS Spectre XPS MS Mode
AMS Designer with Spectre FX
- Options for AMS Designer with Spectre FX
- Connect Module Usage
Loading Plug-In for Spectre Netlist Compiled Functions (NCFs)
Creating a Testbench
Run Script for xrun
- Tcl File Creation to Probe Behavioral Nodes
Port Bindings between Verilog and SPICE
- Binding Ports using autobus
- Binding Ports using a Port-Bind File
- Binding Ports using a Verilog File
- Binding Ports by Name
Customized Port-Bind Files
- Customized Port-Bind File Examples
- Rules That Apply to Customized Port-Bind Files
ie Statement in an amsd Block for Multiple Power Supply Design
- Supply Value to Apply to a Library, Cell, or Instance
- Cadence-Installed Connect Rules Customization
- Cadence-Provided Connect Rules
Block-Based Discipline Resolution for Multiple Power Supply Design
- Connect Modules, Connect Rules, and Discipline Definitions
- Custom Connect Modules, Connect Rules, and Disciplines on the Command Line
Supply-Sensitive Modules for Multiple Power Supply Designs
- Supply-Sensitive Connect Modules
- Supply-Sensitivity Attributes to an Ordinary Module
Interface Elements for Multiple Power Supply Designs
Illustrating the xmelab Process
Access to Digital Simulation Objects
Binding During Mixed-Signal Design Elaboration
Delay Modes in Mixed-Signal Designs
Guidance for Specifying Disciplines for Scopes
Precedence of Discipline Specification Methods
Setting Block-Based Discipline Resolution Specifications in Search Libraries
Setting Pulse Controls for Mixed-Signal Designs
Simulation Front End (SFE) Parser
- Including Structural Verilog-A in a Spectre Netlist
- Using SPICE and Spectre User-Defined Functions
- Using Simplified Input Commands with the Simulation Front End Parser
- Migrating from the Old Spectre Parser
Running the Simulator
Starting or Resuming a Simulation
Restarting the Simulator from a Previously-Saved Snapshot
Use Model 1 (Warm Restart)
Use Model 2 (Cold Restart)
Using the Save-and-Restart Feature
Mixed-Signal Activity Statistics
Other Tasks During Simulation
Exiting the Simulation
Specifying a Host for Spectre
Managing Analog Resource Usage During Interactive Simulations
The Design Browser Window for AMS Designs
Invoking SimVision
SimVision Window Menu Bar
-
Setting Display Preferences for Verilog-AMS Objects
-
Setting Formatting Preferences for Verilog-AMS Objects
Editing Source Information Using the Source Browser
Plotting Signals in the Waveform Window
The Console Window
Cross-Probing Instances and Nets
- Cross-Probing Instances
- Cross-Probing Nets
Analog Mnemonic Maps in SimVision
- Analog Mnemonic Map Application
-
- Limitations
-
- Example
-
Real Value Probe Filtering
Terminology
Downgrading Mixed-Signal Initialization Errors
Forcing and Releasing Signal Values
Managing Breakpoints
After setting breakpoints, you can display information on breakpoints, disable breakpoints, enable previously disabled breakpoints, and delete breakpoints.
Managing Databases
- Opening a Database
- Displaying Information about Databases
- Disabling a Database
- Enabling a Database
- Closing a Database
Mixed Network Debugging
Model Hierarchy for Spectre AMS Designer
Paths and Mixed-Language Designs
Setting and Deleting Probes
- Setting a Probe Using the Tcl probe Command
- Displaying Information about Probes Using the Tcl probe Command
- Disabling a Probe Using the Tcl probe Command
- Enabling a Probe Using the Tcl probe Command
- Deleting a Probe Using the Tcl probe Command
Stepping through Lines of Code
Breakpoints
- Setting a Condition Breakpoint
- Setting a Line Breakpoint
- Setting a Signal Breakpoint
- Setting a Time Breakpoint
- Setting a Process Breakpoint
- Setting a Subprogram Breakpoint
Depositing Values to Signals
Displaying Information about Simulation Objects
Displaying the Drivers of Signals
Automatically-Inserted Connect Modules
Waveforms
- Creating a Database and Probing Signals
- Opening a Database with $shm_open
- Probing Signals with $shm_probe
- Opening the SimVision Waveform Window
Displaying Debug Settings
Setting Variables
Editing a Source File Using Your Own Editor
Searching the Source Code
Searching for a Line Number in the Source Code
Searching for a Text String in the Source Code
Saving and Restoring Your Simulation Environment
Creating or Deleting an Alias
Getting a History of Commands
Managing Custom Buttons
Using Real Number Modeling in SystemVerilog
Specifying Built-In SystemVerilog Nettypes
Specifying User-Defined Nettype and Resolution Function
Resolving Wreal Nets of Built-In Nettype
Handling Port Connections of Nettypes
Wreal Interaction with Built-In Real Nettypes and Real Nettypes with Resolution Functions
Wreal Interaction with Nets of Built-In Nettype
SystemVerilog Interconnects
Port Connection Rules
Port Collapsing Rules
Interconnect Connections to VHDL Ports
Discipline Resolution
Net Delays on Interconnects
SystemVerilog User Defined Nettype and Electrical Connections
Using the Built-In EE Package Connect Modules for UDN-to-Electrical Connections
Using Custom User-Defined Nettype and Connect Modules for UDN-to-Electrical Connections
Enabling Net Aliasing for SV-UDN Connections
Wreal Connections with Concatenated Nettypes to Array of Instances
Example 1
Example 2
Example 3
Example 4
Limitations
Wreal Connections with Concatenated Wires and Nettype Ports
SystemVerilog Binding on SPICE
Wildcard-Named Port Connections in AMS
SystemVerilog Assertions on real, wreal, and electrical Nets
SystemVerilog Assertions
Analog System Tasks in SVA
Using Custom ie Parameter and Connect Module Names for UDN-to-Electrical Connections
Configuring SV-AMS Connect Modules for UDN-UDN, UDN-Logic, and UDN-Real Connections
Complex Port Definitions with User-Defined Nettypes
Using the SVAMS Parser
Variable To Wire (VTW) Optimization in Mixed-Signal Designs
Features Enabled Using the -adv_ms Option
Connecting SystemVerilog Logic Ports to Electrical Using Wire/Interconnects
Connecting SystemVerilog Variable Logic Vector to SPICE Bus
Applying Bit-Wise Discipline for SPICE Bus Connections
Features Enabled Using the -sv_ms Option
Connecting SystemVerilog Hierarchical UDT to Electrical
Coercion for SystemVerilog Interfaces, Program, or Checker Blocks
Using Wildcard‐Named Port Connections in SV Bind Statements
Connecting SystemVerilog Interface to DMS/Verilog-AMS (Electrical) Signals
Connecting SystemVerilog Multi-Dimensional Array to SPICE/Electrical Ports
Build Time & Run Time Performance Improvement for Mixed Signal Designs
Using Common Power Format in Mixed-Signal Designs
Power-Smart Connect Modules for CPF
Support for Multiple Digital Drivers
ie Card Parameters for Power-Smart Connect Modules
Power Aware Modeling in Common Power Format
Connecting Design Supply Net to CPF Power Domain and Design Net
Support for Transition Slope of Power Supply in CPF-Controlled Analog Block
- Referring to the Power Supply of Smart IE from Analog Side Locally
Checking Conflicting Power Domains on Mixed-Signal Boundary
Using wreal Data Type in Mixed-Signal Designs with CPF
- Power Corruption on the Boundary Port of a Wreal Model
- Wreal Expressions in CPF
Specifying Boundary Ports and Macro Models
Using Electrical Expressions in CPF
Feedthrough Wire Analysis
Using the IEEE 1801 Standard in Mixed-Signal Designs
Power Smart Connect Modules for IEEE 1801
Specifying Power Intent on Mixed-Signal Blocks
Power-Aware Analog/RNM Blocks
Specifying Parameter Values for Connect Modules on Power Supply Nets
Automatic Supply Connections in Mixed‐Signal Designs with Liberty Model
- Enabling Automatic Supply Connection in Designs with Higher HDL Connections
- Enabling Automatic Supply Connection in Designs Using Liberty Models with a Default VCT Value
Enabling SystemVerilog Interface in LP-MS Designs
Instantiating Verilog-AMS and VHDL-AMS in SystemC
Preparing and Using Wrappers and Shells
Preparing Interface Modules
- Example: Interface Module for Connecting SystemC Double to Verilog-AMS Electrical
Guidelines for Using AMS Modules in SystemC Models
The xmshell Command
- xmshell Command Syntax
- xmshell Command Options
- Examples of the xmshell Command
Use Models of Incremental Elaboration
Partitioning for UVM Test Modifications
Partitioning for a Stable DUT
Flexible Partitioning for Complex SOCs
Unsupported Scenarios of Incremental Elaboration for Mixed-Signal
Limitations of Incremental Elaboration for Mixed-Signal
Incremental Elaboration at SV-RNM Partition Boundary
Auto-Partitioning Designs with SV-RNM Ports
Coercion of User-Defined Nettype (UDN) across Partition Boundaries
Incremental Elaboration in Designs with UNL Netlists
Incremental Elaboration in OOMR Connections
Incremental Elaboration in Low-Power Mixed-Signal Designs
Cloning of Replicated Modules
analog
- analog Command Syntax
- analog Command Options
call
- call Command Syntax
- call Command Options
- call Command Arguments
- call Command Examples
deposit
- deposit Command Syntax
- deposit Command Options
- deposit Command Example
describe
- describe Command Syntax
- describe Command Options
- describe Command Examples
drivers
drivers Command Syntax
drivers Command Options
drivers Command Examples
drivers Command Report Format
- Verilog Signals
- VHDL Signals
exit
exit Command Syntax
exit Command Options
finish
- finish Command Syntax
- finish Command Options
- finish Command Examples
force
- force Command Syntax
- force Command Options
- force Command Examples
get_analog_param
get_analog_param Command Syntax
get_analog_param Command Options
probe
- probe Command Syntax
- probe Command Options
- probe Command Examples
Probing Built-In and User-Defined Nettypes
Probing SPICE Ports
release
- release Command Syntax
- release Command Options
- release Command Examples
reset
- reset Command Syntax
- reset Command Options
- reset Command Example
restart
- restart Command Syntax
- restart Command Options
- restart Command Limitations
- restart Command Examples
run
run Command Syntax
run Command Options
run Command Examples
save
save Command Syntax
save Command Options
save Command Examples
scope
- scope Command Syntax
- scope Command Options
- scope Command Example
set_analog_param
set_analog_param Command Syntax
set_analog_param Command Options
status
- status Command Syntax
- status Command Options
- status Command Example
stop
- Syntax
- Modifiers and Options
- Example
- Tcl Expressions as Arguments
strobe
- strobe Command Syntax
- strobe Command Options
- strobe Command Examples
time
- time Command Syntax
- time Command Options
- time Command Examples
value
- value Command Syntax
- value Command Options
- value Command Example
where
- where Command Syntax
- where Command Options
- where Command Example
Specifying Unnamed Branch Objects in Tcl Commands
Verilog-AMS Protection
Protection Guidelines for Automatically Inserted Connect Modules
Forced Use of CMI 3.0
Using xmprotect for Source Protection
Examples of Using the Protection Pragmas
Protecting All Modules in a Source Description
Using spectre_encrypt for Source Protection
- The spectre_encrypt Command
Mixed-Signal Simulation Summary
Digital Simulation Profile Results
Analog Simulation Profile Results
string prop sourcefile Translation
cell, inst, and path Translations
cell
inst
path
Stub Instance Translations
default Translations
string prop hdl_cell Translation
string prop sim_stub Translation
string prop sourcefile_opts Translations
