With system-on-chip (SoC) design becoming increasingly more complex, and as process geometries continue to shrink, advanced power reduction strategies such as power shutoff (PSO), multi-voltage threshold (MVT) transistors, and dynamic voltage frequency scaling (DVFS) are now often required for low-power verification.
To support advanced power reduction in EDA tools, two power intent languages were developed. The Unified Power Standard (UPF) was approved by IEEE as the IEEE 1801 Standard and the Common Power Format (CPF) was approved by the Si2 coalition. These languages enable you to define the power intent for a design using semantics and constructs in a separate power intent file (UPF or CPF) independent of the hardware description language (HDL). All power-related specifications, constraints, and functional requirements are specified in this one file and these are then considered during the simulation, verification, and implementation of a design.
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You can specify the power intent using either the IEEE 1801 standard or CPF, but not both.
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To enable the IEEE 1801 flow, you must add
-lps_1801 <file>.upfon thexrunorxmelabcommand line. -
To enable the CPF flow, you must add
-lps_cpf <file>.cpfon thexrunorxmelabcommand line.
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