The Spectre AMS Designer Simulator features a consistent mixed-signal DC initialization for the following analyses using all supported languages in all simulation flows:
- Info
- AC
- Transient
Supported languages include SPICE, Spectre, Verilog-A, Verilog-AMS, and VHDL-AMS. Supported flows include the analog design environment (ADE), the AMS Designer environment, and AMS in verification.
Mixed-signal DC is an AMS simulation process that iterates between analog DC analysis and digital simulation at time 0 until all signals at the analog or digital boundary reach steady state. Any info, AC, or transient analysis you request in your analog simulation control file begins with a mixed-signal DC initialization, whether you request it explicitly (using oppoint, for example) or implicitly (by specifying a transient analysis, for example).
With mixed-signal DC initialization, you get consistent simulation results when you change a module's view (from Verilog to SPICE, for example). The AMS designer simulator correctly reflects the digital signal (stimulus) of a Verilog view in the behavior of analog analyses such as DC, AC, and transient. For example, you can have a design that has a digital Verilog module feeding a Verilog-A or SPICE subcircuit of an analog filter where the digital signal controls the pole and zero positions of the analog filter.
The AMS Designer simulator with Spectre solver executes the code inside @initial_step during all analog or digital DC iterations for mixed-signal initialization of transient analysis.
The default maximum number of mixed-signal DC iterations differs depending on which solver you are using as follows:
|
Solver |
Default Maximum Number of Mixed-Signal DC Iterations |
|---|---|
|
Spectre |
100 |
|
APS |
100 |
You can control the maximum number of mixed-signal DC iterations by setting the AMS_DC_MAX_ITER environment variable as follows:
setenv AMS_DC_MAX_ITER = numIterations
For example, to specify a maximum of five iterations,
setenv AMS_DC_MAX_ITER = 5