Power-Aware Analog/RNM Blocks

Support for the IEEE 1801 standard is available on a mixed-signal network in which a low power-aware signal path is correctly interpreted between the digital and analog driver/receiver, and a low power-aware supply connection is correctly established to connect both analog and digital power supplies.

The connect_supply_net command in IEEE 1801 has been enhanced to support the connection of mixed signal network.

connect_supply_net net_name -ports { port_list }

Signals in port_list with type logic and supply_net_type are handled by UPF and AMS-LPS processing ignores these signals automatically.

UPF supply nets can be connected to design supply nets such as electrical, wreal, and SV-Real Number Modeling (SV-RNM) nets using the connect_supply_net command. This is a unidirectional connection, where the voltage info of the UPF supply nets propagates to design supply nets; and, the power state info on the UPF supply nets are ignored. You can enable this feature using the xrun option, -lpa_ams_uca at the command line.

Additionally, the UPF supply nets and design supply nets can be bidirectionally connected using the xrun option, -lps_ams_connect_supply.  The bidirectional connect module, ER_bidir is automatically inserted on the boundary of UPF and design. This allows the voltage info of the UPF supply nets to propagate to the design supply nets.

In the bidirectional connection, the IEEE 1801 command create_hdl2upf_vct converts the analog voltage in the design to IEEE 1801-defined supply net value and state. Low power-aware connect modules are now aware of the dynamic power supply and convert the signals from logic to electrical accordingly. For example:

create_hdl2upf_vct VCTR2U -hdl_type {sv cds_rnm} -table { {Expression PowerNetState} ... }

connect_supply_net SUPPLY_NET -ports { powr_list } -vct VCTR2U

Here, cds_rnm is a reserved keyword to allow real number content in the -table argument. It indicates the mapping of real-valued expressions to the IEEE 1801 supply nets for lower power simulation.

The datatypes for SV-UDN can be real (real, realtime), logic (bit, logic, reg), integer (int) and enum. And, you need to specify the element of SV-UDN structure. For example:

create_hdl2upf_vct vct_name -hdl_type { sv UDN.RealElement } -table {{real_expression state_value}*}

The expression contains an operator and a value. Following operators are supported:

• Relational: > , >= , < , and <=

• Logical Equality: == and !=

• Case Equality: === and !==

The value can be a real number, `wrealXState, or `wrealZState. The case equality operators can contain only `wrealXState, or `wrealZState as values. Variables or parameters are not supported in HDL code.

Mappings with == and === take the highest priority, whereas mappings with != and !== take the lowest priority. In addition, mappings with the greatest threshold for > or >== or lowest threshold for < or <= take the highest priority.

UPF supply nets must have state and voltage. The UPF state can be UNDETERMINED, PARTIAL_ON, FULL_ON, OFF. 
wreal and electrical ports computed by RNM or Verilog-AMS or Spectre/SPICE model provide only the voltage and no UPF state. When such port drives a UPF supply net, a UPF VCT (Value Conversion Table) must be defined and set at the connection definition. The VCT creates the UPF states for the UPF supply net.
The following example illustrates that when an LDO instance is simulated (in Spectre or SPICE), the LDO output, named vout11 in SPICE sub-circuit, drives a UPF supply net named VDD11sn:

# CREATE A UPF SUPPLY NET
create_supply_net VDD11sn
# DEFINE VALUE CONVERTION TABLE CONVERTING REAL VALUES INTO net_state_type UPF VALUES
create_hdl2upf_vct VCTR2U_VDD11 -hdl_type {sv cds_rnm} \-table { {>=1.0 FULL_ON} {>=0.5 PARTIAL_ON} {<0.5 OFF} } 
# IT IMPORTANT TO ATTACHED THE VCT ONLY TO SUCH CONNECT STATEMENT BECAUSE IT TOUCHED A TRUE SPICE ELECTRICAL PORT
connect_supply_net VDD11sn -ports {I0_top_ana/LDO_SPICE/vout11} -vct VCTR2U_VDD11
# THE RESULT WILL BE THE FOLLOWING
# WHEN V(I0_top_ana/LDO_SPICE/vout11) > 1.0 THEN the UPF VDD11sn WILL BE IN “FULL_ON” state.
# ELSE IF V(I0_top_ana/LDO_SPICE/vout11) >=0.5 THEN the UPF VDD11sn WILL BE IN “PARTIAL_ON” state 
# ELSE IF V(I0_top_ana/LDO_SPICE/vout11) <0.5 THEN the UPF VDD11sn WILL BE IN “OFF” state.

Also, the power state info on the UPF supply nets can be converted to an analog voltage in design using the IEEE 1801 command, create_upf2hdl_vct, has also been enhanced to describe the mapping from the power net to the voltage gate value, as shown in the following example:

create_upf2hdl_vct VCTU2RGND -hdl_type {sv cds_rnm} -table {{OFF `wrealZstate} {UNDETERMINED `wrealXState} {FULL_ON 0}}

connect_supply_net GND -ports { powr_list } -vct VCTU2RGND

• If the power state is OFF, the simulator applies a value `wrealZState on the mixed-signal supply net;

• If the power state is UNDETERMINED, the simulator applies a value `wrealXState on the mixed-signal supply net;

• If the power state is FULL_ON, the simulator applies a value 0 on the mixed-signal supply net.

For VCT definitions in UPF for SV-UDN connections, you need to specify the element of SV-UDN structure. For example:

create_hdl2upf_vct vct_name -hdl_type { sv UDN.RealElement } -table {{real_expression state_value}*}

The datatypes for SV-UDN can be real (real, realtime), logic (bit, logic, reg), integer (int) and enum. And, you can apply VCTs on multiple SV-UDN fields with same datatype. For example:

create_upf2hdl_vct VCTS2V -hdl_type {sv EEnet.V} \
-table { {FULL_ON 1.5} {OFF 0.0} }
create_upf2hdl_vct VCTS2I -hdl_type {sv EEnet.I} \
-table { {FULL_ON 0.001} {OFF 0.0001} }
create_upf2hdl_vct VCTS2R -hdl_type {sv EEnet.R} \
-table { {FULL_ON 100} {OFF 50} }

connect_supply_net vdd -ports {i_ana2/vdd} -vct VCTS2V
connect_supply_net vdd -ports {i_ana2/vdd} -vct VCTS2I
connect_supply_net vdd -ports {i_ana2/vdd} -vct VCTS2R

If there is a supply connection specified in Verilog model, the tool applies a connection between the RTL and UPF signal. If the same port name exists in UPF and HDL models, a connection is established on the UPF supply port.

In the following example, tool applies a connection between UPF supply net VDD and HDL net ipmu/VDD. 

----------tb.upf-----------------------------------
load_upf top.upf -scope dut
create_supply_net VDD
connect_supply_net VDD -ports {dut/VDD}   // connecting to UPF
connect_supply_net VDD -ports {ipmu/VDD}  // connecting to HDL
----------top.upf---------------------------------
create_supply_port VDD
create_supply_net VDD
connect_supply_net VDD -ports {VDD}       // connecting to UPF
connect_supply_net VDD -ports {iainv/VDD} // connecting to HDL 
                                          // optimized away since the HDL signal  “iainv/VDD” is connecting to “ipmu/VDD” in HDL scope.
connect_supply_net VDD -ports {iwinv/VDD} // connecting to HDL
                                          // optimized away since the HDL signal  “iwinv/VDD” is connecting to “ipmu/VDD” in HDL scope.
-----------------tb.sv----------------------------
module tb();
 pmu  ipmu(VDD);
 top  dut(VDD);
endmodule;
----------------top.vams---------------------
module top(VDD);
 ainv  iainv(VDD);
 winv  iwinv(VDD);
endmodule

Additionally, SV-UDN connections can be used in IEEE1801 power supply connection with Liberty model. The datatypes for SV-UDN can be real (real, realtime), logic (bit, logic, reg), integer (int) and enum.

As SV-UDN has multiple fields, you must specify multiple VCTs on same UDN net, to specify the value conversion for power state and voltage.

The following is an example of the HDL source, VCT definitions for the UPF supply nets, and the liberty model. The tool applies the supply connection on SV-UDN net automatically based on the UPF description. The specified VCT is used for value conversion of the specified field.

--------------------HDL Source Code----------------------
module dut();
ana1 i_ana1();
endmodule

module ana1(vdd, vss);
output wTsum vdd, vss;
end
endmodule

--------------------UPF Definition----------------------
connect_supply_net vdd -ports {i_ana1/vdd} -vct VCTR2V
connect_supply_net vdd -ports {i_ana1/vdd} -vct VCTR2S_VDD
connect_supply_net vss -ports {i_ana1/vss} -vct VCTR2V
connect_supply_net vss -ports {i_ana1/vss} -vct VCTR2S_VSS

--------------------Liberty Model----------------------
library ("AMSLPS_TEST") {
cell ("ana1") {
pg_pin (vss) {
pg_type : "primary_ground";
voltage_name : "VSS";
}
pg_pin (vdd) {
pg_type : "primary_power";
voltage_name : "VDD";
}
}
}
--------------------Elaboration Result----------------------
Liberty Verbose Information

ana1 : ana.lib:88
<PA>: ./dut.sv:8
Instances:
tb.i_dut.i_ana1
<E> vss <primary_ground> : vss <VCTR2S_VSS>
<E> vss <primary_ground> : vss <VCTR2V>
<E> vdd <primary_power> : vdd <VCTR2S_VDD>
<E> vdd <primary_power> : vdd <VCTR2V>

Liberty / HDL Matching Information
No mismatch found between Liberty pins and corresponding Verilog ports.