Power Aware Modeling in Common Power Format

A set of built-in Verilog system tasks and VHDL procedures can be used in Verilog (-AMS) or VHDL(-AMS) code to obtain information about the low-power simulation. Most of the tasks / procedures link a Verilog register or a VHDL signal to some low-power information, such as the power-down state of a power domain, the name of the power mode that a domain has just entered, the voltage that a power domain is at after a nominal condition transition, and so on.

Following are the Verilog system tasks and functions:

$lps_get_power_domain(<power_domain_register>[, <instance>]);
$lps_link_power_domain_powerdown(<link_register> [,<power_domain>);
$lps_link_power_domain_standby(<link_register>[, <power_domain>]);
$lps_link_power_domain_voltage(<link_variable>[, <power_domain>]);
$lps_link_power_domain_gnd_voltage(<link_variable> [, <power_domain>]);
$lps_link_power_domain_nmos_voltage(<link_variable> [, <power_domain>]);
$lps_link_power_domain_pmos_voltage(<link_variable> [, <power_domain>]);
$lps_link_power_domain_nominal_condition(<link_register> [, <power_domain>]);
$lps_link_power_domain_power_mode(<link_register> [, <power_domain>]);
$lps_enabled();
$lps_get_stime();

One limitation of low power system task is that you cannot use them inside an analog procedural block. For example, the following module definition will not work because the low-power system task $lps_enabled() is used inside the analog procedural block.

module top (out);
  inout      out;
  reg        temp = 0;
  electrical out;
  real p; 

  initial
    begin
      #10 temp = 1;
    end 

  analog
    begin
      if (!$lps_enabled && (temp == 0))
        p = 0.0;
      else
        p = 3.0;
        V(out) <+ p;
    end 

endmodule

Related Topic

• Power Aware Modeling