Probing SPICE Ports

The following table displays the Tcl probe command options that can be used to probe signals inside the SPICE hierarchy.

Probe Options Supported in SPICE Scope

`-create`	`-shm`	`-database` `dbase_name`	`-all`
`-depth`	`-domain`	`-emptyok`	`-exclude`
`-flow`	`-name` `probe_name`	`-ports`	`-screen [-format] [-redirect]`
`-waveform`	`-delete`	`-disable`	`-enable`
`-save`	`-show`	`-vspice_cell`

Tcl probing inside the SPICE hierarchy is not supported on the AIX platform.

Probing SPICE Ports in Verilog/SPICE Boundary

You can use the -vspice_cell option with the Tcl probe command to probe voltage, current, or both on SPICE ports on Verilog/SPICE or VHDL/SPICE boundary. Consider the following examples:

xcelium> probe -database ams_database -vspice_cell

The above command performs voltage probe on the SPICE ports on Verilog/SPICE boundary.

You can use the -flow and -all options with the -vspice_cell option, to probe both voltage and current, as follows:

xcelium> probe -database ams_database -vspice_cell -flow

The above command performs current probe on the SPICE ports on Verilog/SPICE boundary.

xcelium> probe -database ams_database -vspice_cell -flow -all

The above command performs both voltage and current probes on the SPICE ports on Verilog/SPICE boundary.

When you use the save or .probe commands, then internal SPICE nets as well as SPICE sub-hierarchies are also probed despite using the -vspice_cell option. Therefore, you need to either modify or disable all save and . probe commands in the design to effectively use the -vspice_cell option.
The -vspice_cell option takes precedence over other Tcl probes that refer to the same design hierarchy and are ignored.
Verilog ports are not probed on Verilog/SPICE boundary for SPICE-in-Middle and SPICE-on-Top cases.

Probing SPICE Ports

Probing SPICE Ports in Verilog/SPICE Boundary

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