Specifying Boundary Ports and Macro Models

Boundary ports are specified and applied to primary inputs or outputs of a top-level design or a macro model.

If a mixed-signal net is connected to a boundary port, AMS-CPF ensures that the:

• ISO device is inserted into the boundary port

• ISO device correctly connects with the digital port of the connect module

During the elaboration phase (xrun -elaborate), AMS-CPF:

• replaces the regular connect module with the power smart connect module if the digital side or the analog side is specified as a boundary port

• creates an isolation device for the AMS Boundary port if the driver and load belong to different digital and electrical scopes

• connects the ISO device with the digital side of the connect module during driver-receiver segregation

During the simulation phase (xrun -r), AMS-CPF checks the power status of the boundary port domain in the amscpf-vpi function.

Bus, bit-select, and part-select of an analog port, including the SPICE port, can be used in the boundary port while performing domain mapping, especially for macro model usage, as shown in the following example:

//SPICE block
.subckt ana_inv in[3] in[2] in[1] in[0] out[3] out[2] out[1] out[0] vdd vss
...
.ends ana_inv
//instantiation in top
module top();
...

wire [3:0]data1;
wire [3:0]data2;
wire [3:0]aout1;
wire [3:0]aout2; 

ana_inv anaInst1 (data1, aout1, vdd, gnd);
...
endmodule
//Verilog ref block
module ana_inv (in,out,vdd,vss);
input [3:0]in;
output [3:0]out;
electrical [3:0]in;
electrical [3:0]out;
...
endmodule

The boundary port of a SPICE instance can be defined in the CPF file as follows:

# design ana_inv
set_macro_model ams_inv
create_power_domain -name PD_ON -boundary_ports { vdd vss } -default
create_power_domain -name PD_SW -boundary_ports { in out[3] out[2:1] out[0] }
end_macro_model

Here,

• The whole bus port, such as in, can be specified.

• Part-select of a bus port is supported. For example, out[2:1].

  The index order of the part-select expression should be in the same direction as the bus definition. out[1:2] would be illegal in the above example.

• Bit-select of a bus port is supported. For example, out[0].