SystemVerilog Interconnects

SystemVerilog (SV) interconnect nets are specified using the keyword interconnect and can be used only in net_lvalue port expressions. These are also called explicit interconnects. In addition, there are interconnect nets, also called implicit interconnects, that that are declared as wires but through analysis the elaborator determines whether they should be treated as interconnect nets. Implicit interconnect nets are not declared using the interconnect keyword. SV supports both types of interconnect nets.

An implicit interconnect is considered an interconnect net, if it meets all of the below criteria:

• The net is declared as wire, tri, wand, triand, wor, or trior

• The net is used only in net_lvalue port expressions

• The net is either singular or a packed/unpacked array with a single dimension

• The net is used in concatenation expressions as actual or formal of a non-collapsible port association
• The net does not connect to a variable or expression with any of the following data types:
  • string
  • event
  • chandle
  • unpacked struct that is not supported in the nettype declaration

In general, explicit interconnects can only be connected to nets. However, they can be connected to non-nets under the following conditions:

• If an interconnect connects to both non-nets and nets, the nettype of the interconnect is the nettype of its net connections:
  • If all its connections (both net and non-net) do not have assignment-compatible datatype, an error is generated
  • If its net connections do not have an equivalent nettype, an error is generated

• If an interconnect connects only to non-nets:
  • If the datatypes of all the non-net connections are not assignment-compatible, an error is generated
  • If all the non-nets have real datatype, the nettype of the interconnect is the built-in real nettype with the resolution CDS_res_wreal1driver
  • If all the non-nets have assignment-compatible non-real datatype, the nettype of the interconnect is an implied unresolved nettype with the datatype of the non-nets
  • If the non-nets have non-equivalent datatypes that are assignment-compatible, one of the datatypes is chosen for the implied unresolved nettype

Explicit interconnects are supported in the AMS CPF flow. For explicit interconnects, the following is supported:

• Power domain information on the interconnect net

• Creation of boundary port information on the interconnect net

• Power-smart IE (R2L/L2R/RL_Bidir, R2E/E2R/ER_Bidir) connections to the interconnect net

• Power state propagation on mixed-signal boundary

• Power domain voltage check on mixed signal boundary

The following is not supported:

• Power corruption on interconnect net

• Automatic power supply on interconnect nets

• Interconnect nets in power event control condition

Explicit interconnects can be connected to any port expression that adheres to the following port connection rules:

Port Connection Rules

A singular interconnect can connect to any of the following:

• Singular net of user-defined nettype

• Scalar electrical net

• Singular wreal

• Singular built-in logic net

Connection of a singular interconnect to an array port, or an array port to a singular interconnect is governed by the following rules:

• If an interconnect array is connected to an SV array net of user-defined nettype, both upper and lower port expressions must have the same number of elements. You can use the xrun option -nettype_port_relax to make the upper and lower port expressions have different number of elements.

• If an interconnect array is connected to a wreal array, the upper and lower port expressions may have different numbers of elements.

• If an interconnect array is connected to an electrical bus, the upper and lower port expressions may have different numbers of elements.

• If an interconnect array is connected to a packed built-in logic net array or structure, the upper and lower port expressions may have different numbers of elements.

• If an interconnect array is connected to an unpacked built-in logic net array, both upper and lower port expressions must have the same number of elements.

• An interconnect array cannot be connected to an unpacked built-in logic net structure.

• If an interconnect array is connected to a variable array, both upper and lower port expressions must have the same number of elements.

• If an interconnect array is connected to a non-collapsible array expression, both upper and lower port expressions must have the same number of elements.

Port Collapsing Rules

When a port connection contains an interconnect net, the following collapsing rules apply:

• If either the inner or outer net is an interconnect and the other is a net with a declared nettype (either user-defined or built-in), the dominating net is the net with a declared nettype.

• If both inner and outer nets are interconnects, then the outer net is the dominating net.

However, if you use the -delay_wire_dominant option, the port collapsing rules would be as follows:

• If either inner or outer net is an interconnect net, and the other is a net with a declared nettype, then:
  • If both have a specified delay value, the dominating net is the net with a declared nettype.
  • If only one of them has a delay value, the dominating net is the one with the delay value.
  • If neither of them has a delay value, the dominating net is the net with a declared nettype.

• If both the inner and outer nets are interconnect:
  • If both have a specified delay value, the dominating net is the outer net.
  • If only one of them has a delay value, the dominating net is the one with the delay value.
  • If neither of them has a delay value, the dominating net is the outer net.

Interconnect Connections to VHDL Ports

Explicit interconnects can be connected to VHDL real ports by coercing the interconnect to wreal. In addition, explicit interconnects can be connected to VHDL real ports by coercing the interconnect net to a built-in real nettype. The resolution for explicit interconnects is the same as implicit interconnects. That is, if an explicit interconnect is also connected to a wreal or a net of built-in nettype, it takes that type, otherwise, it gets the default type.

For nets that have a mix of wreal and VHDL real signals, the resolution may change depending on where the drivers of the mixed language net exist. If all the drivers are in VHDL, the resolution is also done in VHDL. If the net has any Verilog drivers, then the resolution is done in Verilog (wreal resolution). If the VHDL and wreal resolution functions do not match, the behavior may be different based on the design configuration.

Explicit interconnects connected to VHDL ports are coerced to electrical. In addition, an interconnect connected to a scalar or vector STD_LOGIC port is coerced to a packed array of logic equivalent to a Verilog logic wire.

Discipline Resolution

Explicit interconnects support default, detailed, and block-based discipline resolution.

Net Delays on Interconnects

The AMS Designer simulator supports a single value net delay on explicit interconnects. For implicit interconnects having multiple delay values, the following rules apply:

• If the interconnect is coerced to a non-logic wire type (like real or struct) the net delay is converted to a single net delay that is the largest of the delay values specified.

• If the interconnect is coerced to a logic wire type, the multiple delay values are preserved.

When ports are collapsed, only the delay on the dominating net is applied. Since the typed net is always the dominating net, net delays on interconnects may not be applied. For more information on how interconnect ports collapse, see Port Collapsing Rules.

In addition, when an interconnect (explicit or implicit) is coerced to electrical, the net delay is ignored.

Related Topic

• Handling Port Connections of Nettypes