save Statement

The save statement specifies nodes or signals whose values are to be saved in the output file. This statement supports saving only the voltage of only analog signals.

save signal { signal }

The signal that you specify must be the complete hierarchical name.

Be careful when you specify a signal name that contains language-specific special characters. The name you use on the save statement must be legal in the Spectre language and must map to a name that is legal in the Verilog-AMS language.

The format for the saved signal waveform is determined by the options rawfmt parameter. The location of the database for the saved signal waveform is determined by the options rawfile parameter.

For example, the following statement specifies that the AMS Designer simulator is to save the signal sig found inside the hierarchy specified by top.i1.

save top.i1.sig

The next example illustrates a name mapping complication.

save cds_globals.\\GND!\ // There is a space after the last backslash.

The `cds_globals.\\GND!\ ' name, when mapped to Verilog-AMS, produces ` cds_globals.\GND! ', which is in the required format.

In AMS Flex flow, the ground node does not appear in waveform database as the ground node is always 0 Volt. This is consistent with the Spectre simulator behavior.

save Statement

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