wreal to VHDL Connections

In mixed-signal designs, to map VHDL analog X/Z states with the Verilog wrealZ/X states use the xrun command-line option, -wreal2vhdlmap file.

You can specify the VHDL/wreal X and Z state mappings in a file. The template format is in the form of wreal2vhdlmap card which defines the mapping for the specified VHDL data type. Multiple wreal2vhdlmap cards can be specified in the file. The format of the wreal2vhdlmap card is shown below:

wreal2vhdlmap type=[ "default" | "<vhdl type>" ] \

wrealXState = "<vhdl primary xstate> <vhdl secondary xstate> ......" \

wrealZState = "<vhdl primary zstate> <vhdl secondary zstate>,...."

When type is set to default , it indicates the default mapping, otherwise, type specifies the VHDL type or subtype that needs to be mapped. If a type-based match is not found, the default mapping is used. You can specify only one wreal2vhdlmap card with type=default.

Currently, a simulation run supports only five wreal2vhdlmap card entries.

The wrealXState and wrealZState arguments support a list of values to be mapped. The first element in the list is considered the primary value map and the remaining elements, if specified, are considered as secondary value maps. The primary value map is significant because it defines the value mapping for both Verilog driving VHDL and VHDL driving Verilog. The secondary maps are only used for mapping VHDL driving Verilog. In this form, a one-to-one mapping is supported for Verilog driving VHDL, whereas a many-to-one mapping is supported for VHDL driving Verilog. The wrealXState parameter defines the X state maps while the wrealZState parameter defines the Z state mapping.

When VHDL is driving a primary or secondary value, the value is mapped to the wrealXState or wrealZState value in the Verilog domain. Note that the primary and secondary values specified in wrealXState and wrealZState parameter must be unique, otherwise, a fatal error is reported.

The type argument (except type=default ) is used when an exact match is desired. wreal2vhdlmap card also supports derived mapping. Derived mapping can be performed by specifying the derived_type argument in the wreal2vhdlmap card, as shown below.

wreal2vhdlmap derived_type="<vhdl type>"\

wrealXState = "<vhdl xstate1> <vhdl xstate2> ......" \

wrealZState = "<vhdl zstate1> <vhdl zstate2>,...."

In this mode, the search is extended to the type decomposition of the actual. A match occurs when the specified derived_type matches one of the decomposed types of the actual. Note that the mapping algorithms find the best map where the order of precedence is type mappings, derived_type mappings and default mappings. For derived_type mappings the lookup algorithm binds to the derived_type mapping closest with respect to the decomposition to the actual type.

Example:

The following example shows a VHDL package with type declaration to be mapped to wreal. The constant values represent the VHDL values to be mapped to wreal x and z states. This package myPkg is compiled into the library myLib.

package is myPkgtype analog_ut is range real'low to real'high;
type analog_vector_ut is array (natural range <>) of analog_ut;constant ANALOG_U : analog_ut := analog_ut'left;
constant ANALOG_X : analog_ut := analog_ut(real(analog_ut'left) / 2.0);constant ANALOG_Z : analog_ut := analog_ut(real(analog_ut'left) / 4.0);
end myPkg;

Following is the file that contains the wreal2vhdlmap template for the VHDL type above:

wreal2vhdlmap type="myLib.myPkg.analog_ut" wrealXState = "myLib.myPkg.ANALOG_X myLib.myPkg.ANALOG_U" \

wrealZState = "myLib.myPkg.ANALOG_Z"

This template states that for mixed language boundary net connections of myLib.myPkg, analog_ut connecting to Verilog real, the following mapping occurs:

Verilog driving a wrealXState value will be mapped to a myLib.myPkg.ANALOG_X VHDL value (primary value)

Verilog driving a wrealZState value will be mapped to a myLib.myPkg.ANALOG_Z VHDL value.

VHDL driving myLib.myPkg.ANALOG_X or myLib.myPkg.ANALOG_U value will be mapped to a wrealXState Verilog value.

VHDL driving a myLib.myPkg.ANALOG_Z value will be mapped to a wrealZState Verilog value.

wreal to VHDL Connections

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