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Introduction

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This chapter provides a general overview of Virtuoso Space-based Router and discusses the following topics:

• What is Virtuoso Space-based Router?
• Why Use Virtuoso Space-based Router?
• Key Benefits
• Key Features
  • Platforms/Operating Systems
• Interoperability
• Design Data
  • Connectivity
  • Hierarchy Depth Control
  • Data Size and Performance
  • Data Object Support

What is Virtuoso Space-based Router?

The Virtuoso® Space-based Router enables high-speed shape-based routing, allowing gridded or gridless, and track-based routing of regular and power signals, for physical designs. By using Virtuoso Space-based Router, r, you can quickly and efficiently edit, check, and manipulate interconnects. The hierarchical connectivity extraction and shape model ensures that the edits are design-rule and connectivity correct by default. It comprises a constraint driven routing environment that supports the following features.

• Automatic routing/Signal routing
• Specialty routing
  • Bus
  • Shielding
  • Differential Pair
  • Matched Length
• Power routing
• Pin to Trunk routing

Why Use Virtuoso Space-based Router?

• Space-based Routing Technology
  The physical implementation process including routing is what can make or break your yield and manufacturing objectives. Shapes on the layout not equal to the shapes on the silicon means costly silicon re-spins. To compensate, designers rely on resolution enhancement techniques and density management techniques. They also employ overly conservative rules which result in a die area penalty.
  Virtuoso Space-based router has the capacity and flexibility to help you manage these complex issues simultaneously, greatly reducing mask re-spin costs. Its unique routing architecture is based on a patented space-based approach that meets the manufacturing, lithography, materials, and performance requirements of high-end digital and analog/mixed-signal designs.
  The router models advanced processes and design constraints, providing maximum control and exceptional results up front in the design process for high performance blocks and full chips. It also features specialty mixed-signal routing and design-for-manufacturing and design-for yield optimization.
  Virtuoso Space-based router improves the designs manufacturability and reduces time-consuming post-processing for OPC and copper planarity issues, ensuring that you meet your manufacturing and electrical objectives the first time around. You can specify advanced constraints for high-performance routing such as sophisticated wire tapering, layer control, and noise avoidance. Complex pre-routes, previously done manually, can now be performed automatically.

Licensing Requirements

You can launch the Virtuoso Space-based Router from either the Layout Suite XL or a higher tier. The Virtuoso Space-based routing features use the token-based license scheme under the Layout Suite licenses. The following table lists the features and the Layout Suite levels at which each is available.

VSR further checks out a minimum of 12 GXL tokens in addition to the licenses already checked out.

For information about licensing in the Virtuoso Studio design environment, see Virtuoso Studio Licensing and Configuration User Guide.

Key Benefits

• High capacity without difficulty handles flat and hierarchical data for 250K net designs
• Innovative hierarchical, 3-D, space-based architecture enables accurate modeling, manipulation, and checking of sophisticated geometries and constraints for advanced node designs
• Preserves the art of precision handcrafting while offering the benefits of automation
• Offers an intuitive and simple-to-use interactive and automatic interconnect environment

Key Features

Virtuoso Space-based Router provides the following features for routing your placed design:

• Gridded or Gridless
  • In gridless mode, the edges of all shapes must be on the manufacturing grid.
  • In gridded mode, the centerlines and endpoints of route segments must be on a routing grid and the origins of vias must coincide with the X and Y of a routing grid.
• WSPs, Tracks, and Snap Patterns
  Supports Patterns (WSP) to create tracks in the layout. WSPs are an advanced form of snap pattern definitions (SPDef) that define the tracks on which shapes can be placed. It overall includes the use of orthogonal grids and local regions.
• Tapering
  Virtuoso Space-based Router will taper routing when necessary to connect pins. Tapering can be controlled independently by each constraint group.
• Tie-up and Tie-down Routing for Power Connections

Platforms/Operating Systems

• Sun™ Solaris™ (32-bit, 64-bit)
• Linux^® (32-bit, 64-bit)

Interoperability

Virtuoso^® Layout Suite XL and Higher Tiers Layout Editor

• Speeds physical layout of custom digital, mixed-signal and analog designs at the device, cell, and block levels
• Supports both constraint- and schematic-driven physical implementation
• Native Cadence Space-based Router technology delivers differential, bus, and shielding routing in a single, common cockpit
• Provides constraint-driven enforcement of process and design rules

Design Data

Connectivity

Virtuoso Space-based Router functionality is driven by design connectivity. There are different ways to create routable views with connectivity.

• from LEF/DEF
  For information, see Design Translation Using LEF/DEF Translator in the Design Data Translator’s Reference.
• from a schematic-driven Virtuoso flow
  The Connectivity Extractor allows you to extract the top level of your design, the entire design, or extract to the level of the hierarchy you specify using the extractStopLevel.
  For more information see Preparing Your Design for Routing in the Virtuoso Layout Suite documentation.
• Mixed signal flow
  The analog nets are either routed manually or by using the Virtuoso Space-based Router (VSR) and the signal nets are routed by Cadence® NanoRoute® Advanced Digital Router supported by the Innovus system.

Virtuoso Space-based Router uses rectangles, polygons, paths, segments, and vias to determine connectivity. Shapes not recognized as interconnect include circles, ellipses, and shapes with non-orthogonal angles.

Hierarchy Depth Control

As part of Virtuoso Layout Suite XL and higher tiers, VSR supports hierarchical designs. You can control hierarchy depth for the following.

• Display - set Start and Stop Display Levels in the Display Options form. (Options > Display...)
  This setting controls the range of hierarchy levels displayed in the canvas window.
  
  The setting also controls hierarchy depth for interactive and automatic routing commands including point-to-point, finish routing, and signal routing.
• Routing - set Start and Stop Display Levels in the Display Options form.
• Extraction - set Extract Connectivity to Level in the Connectivity tab of the Connectivity form. (Options – Layout XL...).
  This setting controls the number of hierarchy levels to check when extracting connectivity.
• Interactive rule checking - set Hierarchy Depth in the DRD Options form (Options – DRD Edit...).
  This settings tells the DRD rule checker the level to which to check for violations.

Data Size and Performance

Routing performance depends on several factors such as the number of nets and devices, whether the design is hierarchical or contains abstracted blocks. The three design types supported by Virtuoso Space-based Router are: Microprocessor, Mixed Signal, and Digital SoC (Std Cell & Memory).

Data Object Support

Wiring Objects

• Segments
  All Space-based router functionality supports segments. If you have preroutes that are paths, they remain as paths in the router. However, the router generates only segments.
• Vias
  Interactive and automatic routing support both custom and standard vias and via variants. You can have all standard vias, all custom vias, or a mixture of standard and custom vias.

Pins

Polygon pins are supported as long as the edges are orthogonal or diagonal. Polygons with diagonal edges are broken into octagons.

Blockages

Any non-routing object that does not have connectivity is seen as a blockage. The router supports rectangles and polygons as long as the edges are orthogonal or diagonal. Any angle edges are not supported.

Multipart paths (MPPs)

The Automatic routing does not route MPPs or change them during routing. However, the autorouter can route to MPPs. You can route to MPPs where only one layer is a routing layer, for example a guardring. You cannot route correctly to MPPs containing multiple routing layers because the autorouter does not trace connectivity between layers through via shapes in MPPs.