7

---

Name Mapping

---

To make data interoperable among Cadence^® applications, Cadence developed a common naming convention called name mapping.

The rules for creating legal names within an application define what is called a namespace. Data between Cadence applications is interoperable, as shown below, because Cadence maps names from one namespace to another. Name mapping is consistent and predictable.

The Cadence name mapping system maps names when applications use data from other applications with noncompatible naming conventions.

Sets of Cadence applications can create names in different ways. Therefore, names used for the same design objects (such as nets, ports, instances, libraries, cells, views, and properties) vary across applications.

Importance of Name Mapping

If the Cadence system maps names between products automatically for you, why do you need to know about it?

You need to recognize that some design data appears differently when you use the data in other applications. In other applications, you see the mapped name. The system changes the names to fit each application as a design description moves through a design flow.

When you have to enter names in multiple places of a design flow where the names must match each other, you need to know how to form the corresponding name in multiple namespaces. For example,

• If you are working with a library name that is used in Leapfrog, you use the VHDL namespace.
• If you subsequently use the ncvlog, you use the Verilog namespace
• The library definition in the cds.lib file is in the LibraryUnix namespace.

In other words, a library used in Leapfrog with -work MYLIB is subsequently used in the ncvlog with -lib mylib. This library must be defined in the cds.lib file with a statement such as:

DEFINE mylib /usr/libs/mylibdir

An example of VHDL mapping to Verilog, then to LibraryUnix, and back to VHDL looks as follows:

VHDL	Verilog	LibraryUnix	VHDL
myName1	myname1	myname1	myname1

You also need to be aware that names in applications and names in the file system are in different namespaces. Names in the file system are in the Library namespace. Therefore, a name that you see in the file system might not always be the same as the name that you typed into the application. This usually happens when the original name contains special characters, such as a period, which are changed when the name is mapped to the Library namespace. For example, if you name a view layout.placed, the directory name in your file system is layout#2eplaced.

When you need to use the name in your application (in user interface forms, command-line options, the Command Interpreter Window, or code), do not use the mapped file system name; specify the original name instead.

You can use the nmp command to get the original name for a mapped file system name.

Type the following in a UNIX shell:

nmp mapName Library yourAppNameSpace mappedFileSystemName

For example, if you type the following command:

nmp mapName Library CDBA layout#2eplaced

the nmp command returns the following:

layout.placed

You can avoid name mapping issues by always choosing names that use only lowercase letters and digits.

How Name Mapping Works

To properly handle the variety of names in Cadence applications, each software product applies the correct namespace for each identifier (explained below). A port or pin of an instance might be called i1/addr<3:0> on a Virtuoso^® schematic editor or Concept schematic. In Verilog, this name becomes i1.addr[3:0] and in VHDL it becomes i1:addr(3 downto 0). The parts of these names are as follows:

Name Item	Explanation
i1	An identifier (an instance name in this case)
slash ( / ), period ( . ), colon ( : )	A hierarchy delimiter
addr	An identifier (a port/pin name in this case)
<3:0>, [3:0], (3 down to 0)	An index expression

Related Topics

The nmp Command

Rules for the Name Mapping Algorithm

Name Mapping SKILL Functions

Recognizing Identifiers and Understanding Case Sensitivity

Identifiers are the atomic strings your application chooses to identify a design object uniquely. Identifiers are present in the names of many kinds of design objects. Names of nets, ports, instances, libraries, cells, views, and properties contain identifiers. To handle these names properly as they are referenced in different steps of a design flow, Cadence applications consistently apply the correct namespace for each identifier and follow the name mapping rules wherever names from different namespaces are compared.

The CDBA view specification /chip/core/ALU contains three identifiers: chip, core, and ALU. When you subsequently use this information in another application, the algorithm modifies these identifiers into legal identifiers in the target namespace. For example, in the VHDL namespace these identifiers look like chip, core, and \ALU\. Mapping goes both ways.

Illegal Characters in Identifiers

If an escaped namespace is not available for the target namespace, or if the identifier contains characters that are illegal, the algorithm uses character encoding. Characters that are illegal in the target namespace are replaced with a pound sign ( # ) followed by the character value encoded as two hexadecimal digits (0–9 or a–f); for example, #2a. The identifier a*b is represented as a#2ab in a namespace that does not support the asterisk (*).

Case Sensitivity

Most Cadence applications are case sensitive. However, some namespaces, such as VHDL, Concept, and LibraryNT, are case-insensitive.

To provide a one-to-one map between, for example, Verilog and VHDL, name mapping must provide normal alphabetic names. The Verilog name StopGap becomes StopGap in VHDL and the Verilog name stopgap becomes stopgap in VHDL, so, because VHDL is case insensitive, two different Verilog names become a single VHDL name.

To handle this situation, the name mapping rules map all case-insensitive letters as lowercase case-sensitive letters and vice-versa. Case-sensitive uppercase letters map to escaped names where these are available (VHDL and Concept). In the LibraryNT namespace, the algorithm precedes them with a percent sign ( % ) so that the Verilog name GORP becomes %G%O%R%P.

You can avoid name mapping issues by always choosing names that use only lowercase letters and digits.

Related Topics

The nmp Command

Name Mapping Rules

Rules for the Name Mapping Algorithm

Cadence uses algorithmic name mapping to map identifiers between different namespaces.

• Names can be mapped from one namespace to another using the legal identifier and the source and destination namespaces. The algorithm does not need auxiliary information such as design-specific mapping tables. The algorithm is designed to be context free so that no information about the design is necessary to perform the mapping.
• Every identifier that is legal in one namespace maps to a legal identifier in every other.
• Every pair of identifiers that are different names in one namespace map to different names in every other namespace.
• All mappings are reversible. Mapping an identifier from one namespace to another and then back to the original namespace always results in the original identifier, with the possible exception of a loss of case if the original namespace is case insensitive.

Algorithmic name mapping does not solve certain problems, such as mapping names to another representation where the design has been modified.

Examples of differences between namespaces are as follows:

Differences	Examples of Namespace Rules
Keywords	The string and is a keyword in Verilog and VHDL, while process is a keyword in VHDL but not in Verilog. Many namespaces, such as CDBA and LibraryUnix, have no keywords.
Case Sensitivity	In Concept and VHDL, the identifier aaa refers to the same object as AAA. In CDBA and LibraryUnix, these names are different.
Syntax and Characters	Many namespaces have an alternative way to include characters in names that would otherwise be illegal. In VHDL, \a+b*\ is a legal identifier because the backslashes ( \ ) escape the characters that are otherwise illegal. A normal Verilog name can contain a dollar sign ( $ ), but a VHDL name cannot unless it is escaped.

Related Topics

Name Mapping Rules

The nmp Command

Cadence provides a command called nmp to help you understand name mapping. You can use this command, located in your_install_dir/tools/bin, to see how a name maps from one namespace to another, to check if a name is legal in a particular namespace, or to get a list of all the namespaces that Cadence applications use.

Use the following syntax for the nmp command:

nmp { getSpaceNames | isLegalName nameSpace identifier | mapName fromNameSpace toNameSpace identifier | -v[ersion] | -help }

getSpaceNames	Lists all the namespaces that Cadence applications use.
isLegalName nameSpace identifier
	Checks if identifier is a legal name in the namespace you specify. If you are specifying an escaped name or a name with special characters that the shell might delete, such as a backslash, enclose the name in single quotes. Also, in some shells, you might need to escape the backslash that is part of an escaped name with another backslash.
mapName fromNameSpace toNameSpace identifier
	Maps a name (identifier) from one namespace to another. If you are specifying an escaped name or a name with special characters that the shell might delete, such as a backslash, enclose the name in single quotes. Also, in some shells, you might need to escape the backslash that is part of an escaped name with another backslash.
-v[ersion]	Displays the version of the nmp command.
-help	Displays the syntax and usage of the nmp command.

Examples:

% nmp isLegalName Verilog buf_addr0
legal

% nmp mapName Concept VHDL procedure
\procedure\

Warning: When you enter names with backslashes, the shell might delete a backslash so that it is not seen by the nmp program. To avoid this, include all names in single quotes, such as ’name’. For example:

% nmp mapName VHDL Concept \procedure\ 
**procedure is not a legal VHDL identifier**

% nmp mapName VHDL Concept ’\procedure\’
procedure

Warning: Verilog requires escaped names to end in a space. This space might not be visible in the output. For example:

% nmp mapName VHDL Verilog ’\2+2=4\’
\2+2=4 

% nmp mapName Verilog VHDL ’\2+2=4
’
\2+2=4\ 

Warning: In some shells, you need to escape the backslash that is part of an escaped name with another backslash. For example:

sh% nmp mapName Verilog LibraryUnix ’\!Lib!
’
#21Lib#21 

csh% nmp mapName Verilog LibraryUnix ’\\!Lib!
’
#21Lib#21 

Related Topics

Namespaces for Different Data Types

Rules for the Name Mapping Algorithm

Name Mapping Rules

Cadence applications adhere to the following name mapping rules:

• As much as possible, names are not modified. For example, the identifier abc is left the same in every supported namespace.
• When an identifier contains a character that is illegal in the namespace to which it is being mapped (even using escaping), the algorithm uses the hex value for the character, such as a character with the hex value of 2d (a minus sign) becomes #2d.
• When case-insensitive names are converted to case-sensitive namespaces, the letters are set to lowercase.
• When case-sensitive names are mapped to a case-insensitive namespace, they are left alone if they are lowercase. If they are uppercase, the algorithm creates escaped names if the namespace has a case-sensitive escaped form, such as in VHDL and Concept.
• If an escaped name that is legal and is a different name when the escape characters are left off is mapped to a namespace where there is not a similar escaped form, then the algorithm prepends the characters ESC_ to the mapped name. For example, in VHDL, \aaa\ is a different name from aaa, so they cannot both map to aaa in Verilog. The name mapping rules map a VHDL \aaa\ to ESC_aaa in Verilog.
• Length restrictions are not handled by these name mapping rules. The mapping routines can handle names up to 2,000 characters long.

Examples of Name Mapping

Type	VHDL	Verilog	CDBA	Concept	Library Unix	LibraryNT
lowercaseor case insensi-tive	bigchip BIGCHIP	bigchip	bigchip	bigchip BIGCHIP	bigchip	bigchip BIGCHIP
case-sensitivemixed case	\BigChip\	BigChip	BigChip	\BigChip\	BigChip	%Big%Chip
keyword	\and\	\and	and	and	and	and
unneeded escape	\trash\	ESC_trash	ESC_trash	\trash\	ESC_trash	ESC_trash
embedded space	\foo bar\	\foo#20bar	a#20b	foo bar	foo#20bar	foo#20bar
device names	aux	aux	aux	aux	aux	%%aux
back-slash	\\\a\\b\	\\a\b	#5ca#5cb	‘\a\b’	#5ca#5cb	#5ca#5cb
forward slash	\/a/b\	\/a/b	#2fa#2fb	/a/b	#2fa#2f	#2fa#2fb
special charac-ters*	\a<1:2>\	\a<1:2>	a#3c1:2#3e	“a<1:2>”	a#3c1#3a2#3e	a#3c1#3a2#3e

* Although the special characters look similar to a name with an index expression, this row shows an identifier, with special characters, that is being used as an atomic identifier. The character indicates a blank space.

Avoid Name Mapping Issues

Use these strategies for name handling:

• Choose names that use only lowercase letters, digits, and underscores.
• Use identifiers that start with an alphabetic character.
• Do not use identifiers that are keywords in any of the namespaces.
• Do not use characters that are not allowed in any of the namespaces.

Related Topics

ALT_NMP Namespace

Rules for the Name Mapping Algorithm

Checking the Names in your cds.lib File

Many Cadence applications include the cdsLibEditor tool.

To check the name (for example, for VHDL) in your cds.lib file,

• Type the following command in a shell window:
  

  cdsLibEditor -namespace VHDL

  The Library Path Editor opens, showing you library names in the VHDL namespace. In VHDL, the system maps the library name TEST as test because the library name stored in the cds.lib file is case sensitive.

Related Topics

Creating or Editing a cds.lib File

Namespaces for Different Data Types

Cadence applications use the following namespaces:

• VHDL
• VHDLAMS
• VHDL87
• Verilog
• VerilogA
• VerilogAMS
• ALT_NMP
• CDBA
• CDBAFlat
• Concept
• General Constraint Format (GCF)
• Genesis
• Library Exchange Format (LEF)
• Design Exchange Format (DEF)
• Library
• LibraryUnix
• LibraryNT
• Print
• Standard Delay Format (SDF)
• Standard Parasitic Format (SPF)
• Standard Parasitic Exchange Format (SPEF)
• Spectre
• SpectreHDL
• Spice

Related Topics

VHDL, VHDLAMS, and VHDL87 Namespaces

Verilog, VerilogA, and VerilogAMS Namespaces

SystemVerilog Namespace

ALT_NMP Namespace

CDBA Namespace

Concept Namespace

GCF Namespace

Genesis Namespace

LEF and DEF Namespaces

Library Namespace

Print Namespace

SDF Namespace

SPEF Namespace

SPF Namespace

Spectre Namespace

SpectreHDL Namespace

Spice Namespace

VHDL, VHDLAMS, and VHDL87 Namespaces

Each VHDL identifier is either in the normal form, such as ABC, or the escaped form, such as \ABC\. Most identifiers in a VHDL design are VHDL normal identifiers.

The VHDLAMS namespace is used in the AMS environment. VHDLAMS is identical to the VHDL namespace except that it has additional reserved keywords.

The VHDL87 namespace is used by some VHDL simulators such as NC-VHDL. VHDL87 is identical to the VHDL namespace except that some keywords that are reserved in VHDL are allowed as normal identifiers in VHDL87.

VHDL Normal Names

VHDL normal identifiers are not case insensitive. This means that the identifier AbC and the identifier abc are equivalent and refer to the same object. VHDL normal identifiers can contain alphabetical characters, digits, or the underscore character. The first letter must be an alphabetical character. The only symbol that is allowed is the underscore. Spaces are not allowed.

VHDL Escaped Names

VHDL escaped identifiers are case sensitive, unlike normal VHDL names. Escaped identifiers always begin and end with a backslash (\). This means that the identifier \AbC\ and the identifier \aBc\ refer to two different objects.

An identifier in the VHDL normal namespace and the same identifier in the VHDL escaped namespace do not represent the same object. For example, the VHDL identifiers abc and \abc\ refer to two different objects. To embed a backslash in an escaped identifier, use double backslashes.

If the original identifier was in the VHDL escaped form even though it was legal in the VHDL normal form, it needs to be returned to the escaped form, not the normal form. For example, \abc\ maps to CDBA ESC_abc, and it maps back to \abc\ in VHDL.

All alphanumeric characters and symbols, as well as spaces, are allowed as VHDL escaped identifiers.

Reserved VHDL Keywords

The following keywords are reserved and cannot be used as VHDL identifiers.

abs	component	guarded	nor	record	then
access	configuration	if	not	register	to
after	constant	impure	null	reject	transport
alias	disconnect	in	of	rem	type
all	downto	inertial	on	report	unaffected
allow	element	inout	open	return	units
and	else	is	or	rol	until
architecture	elseif	label	others	ror	use
array	end	library	out	select	variable
assert	entity	linkage	package	severity	wait
attribute	exit	literal	port	signal	when
begin	file	loop	postponed	shared	while
block	for	map	private	sla	with
body	function	mod	procedure	sll	xnor
buffer	generate	nand	process	sra	xor
bus	generic	new	pure	srl
case	group	next	range	subtype

Reserved VHDLAMS Keywords

Reserved VHDL keywords are also reserved in VHDLAMS. In addition, the following keywords are also reserved in VHDLAMS and cannot be used as VHDLAMS identifiers.

across	procedural	terminal
break	quantity	through
limit	reference	tolerance
nature	spectrum
noise	subnature

Reserved VHDL87 Keywords

The following keywords are reserved and cannot be used as VHDL87 identifiers.

abs	access	after	alias	all	allow
and	architecture	array	assert	attribute	begin
block	body	buffer	bus	case	component
configuration	constant	disconnect	downto	element	else
elseif	end	entity	exit	file	for
function	generate	generic	guarded	if	in
inout	is	label	library	linkage	loop
map	mod	nand	new	next	nor
not	null	of	on	open	or
others	out	package	port	private	procedure
process	range	record	register	rem	report
return	select	severity	signal	subtype	then
to	transport	type	units	until	use
variable	wait	when	while	with	xor

Related Topics

Namespaces for Different Data Types

Name Mapping Rules

Verilog, VerilogA, and VerilogAMS Namespaces

Each Verilog identifier is either in the normal form ABC or the escaped form \ABC
. Most identifiers in a Verilog design are Verilog normal identifiers. If you need to represent identifiers that are illegal as a Verilog normal identifier, use the Verilog escaped namespace. For example, the identifier and in the CDBA namespace maps to the Verilog escaped \and
because and is a Verilog keyword.

The VerilogA analog simulator uses the VerilogA namespace. The namespace is the same as the Verilog namespace, except that it has additional reserved keywords.

The AMS environment uses the VerilogAMS namespace. The VerilogAMS namespace is the same as the Verilog namespace, except that it has additional reserved keywords.

Note: The
character in Verilog names is used to clearly document a blank space.

Verilog Normal Names

Verilog normal identifiers are case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects. Verilog normal identifiers might contain letters, digits, the underscore character, and the dollar sign ( $ ). The first character cannot be a digit or a dollar sign ( $ ). All letters and digits are allowed as Verilog normal identifiers. The space is not allowed.

Verilog Escaped Names

Verilog escaped identifiers always begin with a backslash (\) and terminate with a space. Verilog escaped identifiers are case sensitive. This means that the identifier \AbC
and the identifier \aBc
refer to two different objects.

Although any identifier can be escaped, only those identifiers that might not be represented in the Verilog normal namespace due to character restrictions or because they are keywords need to be escaped. An identifier in the Verilog normal namespace and the identifier in the Verilog escaped namespace represent the same object. For example, the Verilog identifiers abc and \abc
refer to the same object.

All alphanumeric characters and symbols are allowed in Verilog escaped identifiers. Blanks or nonprinting characters are not allowed.

Reserved Verilog Keywords

The following keywords are reserved in Verilog and cannot be used as Verilog identifiers.

always	end	ifnone	output	rtranif0	tri
and	endattribute	initial	package	rtranif1	tri0
assign	endcase	inout	parameter	scalared	tri1
attribute	endfunction	input	pmos	signed	triand
begin	endmodule	integer	posedge	small	trior
buf	endpackage	join	primitive	specify	trireg
bufif0	endprimitive	large	pull0	specparam	use
bufif1	endspecify	macromodule	pull1	strength	vectored
case	endtable	medium	pulldown	string	wait
casex	endtask	module	pullup	strong0	wand
casez	event	name	rcmos	strong1	weak0
class	for	nand	real	supply0	weak1
cmos	force	negedge	realtime	supply1	when
deassign	forever	nmos	reg	table	while
default	fork	nor	release	task	wire
defparam	function	not	repeat	time	wor
disable	highz0	notif0	rnmos	tran	xnor
edge	highz1	notif1	rpmos	tranif0
else	if	or	rtran	tranif1

Reserved VerilogA Keywords

The following keywords are reserved in VerilogA and cannot be used as VerilogA identifiers.

above	ddt	final_step	limexp	pullup	tran
abs	ddt_nature	flicker_noise	ln	real	tranif0
absdelay	cosh	flow	localparam	realtime	tranif1
abstol	cross	for	log	reg	transition
access	ddx	force	max	release	tri
acos	deassign	fork	medium	repeat	tri0
acosh	default	from	micromodule	rnmos	tri1
ac_stim	defparam	function	min	rpmos	triand
aliasparam	delay	generate	module	rtran	trior
always	disable	genvar	nand	rtranif0	trireg
analog	discipline	ground	nature	rtranif1	units
analysis	discontinuity	highz0	negedge	scalared	vectored
and	driver_update	highz1	net_resolution	sin	vt
asin	edge	hypot	nmos	sinh	wait
asinh	else	idt	noise_table	slew	wand
assign	end	idtmod	nor	small	weak0
atan	endcase	idt_nature	not	specify	weak1
atan2	endconnectrules	if	notif0	specparam	while
atanh	enddiscipline	ifnone	notif1	sqrt	white_noise
begin	endfunction	inf	or	strobe	wire
bound_step	endmodule	initial	output	strong0	wor
branch	endnature	initial_step	parameter	strong1	wreal
buf	endparamset	inout	pmos	supply0	xnor
bufif0	endprimitive	input	posedge	supply1	xor
bufif1	endspecify	integer	potential	table	zi_nd
case	endtable	join	pow	table_model	zi_np
casex	endtask	laplace_nd	primitive	tan	zi_zd
casez	event	laplace_np	pull0	tanh
ceil	exclude	laplace_zd	pull1	task
cmos	exp	laplace_zp	pulldown	temperature
connectrules	floor	large	pwr	time
cos	forever	last_crossing	rcmos	timer

Reserved VerilogAMS Keywords

Reserved Verilog keywords are also reserved in VerilogAMS. In addition, the following keywords are also reserved in VerilogAMS and cannot be used as VerilogAMS identifiers.

above	abs	abstol	ac_stim
access	acos	acosh	a2d
analog	aliasparam	analysis	asin
asinh	atan	atan2	atanh
attribute	bound_step	branch	ceil
class	connect	connectmodule	connectrules
cross	continuous	cos	cosh
delay	ddt	ddt	ddt_nature
domain	discipline	discontinuity	discrete
driver_local	driver_active	driver_count	driver_delay
driver_strength	driver_next_state	driver_next_strength	driver_state
endattripute	driver_update	dynamicparam	endconnectrules
endnature	enddiscipline	endparamset	endpackage
flicker_noise	exclude	exp	final_step
generate	floor	flow	from
idt	genvar	ground	hypot
initial_step	idt_nature	idtmod	inf
laplace_zp	laplace_nd	laplace_np	laplace_zd
localparam	last_crossing	log	limexp
ln	max	merged	min
nature	net_resolution	noise_table	noshowcancelled
paramset	pathdelay_controlsignal	pathdelay_max0	pathdelay_max1
pathdelay_min0	pathdelay_min1	pathdelay_sense	potential
pow	pragma	pulsestyle_ondetect	pulsestyle_onevent
real2int	resolveto	showcancelled	signed
sin	sinh	slew	split
strength	sqrt	tan	tanh
timer	to	transition	use
using	units	when	white_noise
with	wreal	zi_nd	zi_np
zi_zd	zi_zp

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

SystemVerilog Namespace

SystemVerilog has eight namespaces for identifiers, which includes:

1. Definitions namespace: Merges all the non-nested module, macromodule, primitive, program, and interface identifiers defined outside of all other declarations.
2. Package namespace: Merges all the package identifiers defined among all compilation units. Once a name is used to define a package within one compilation unit the name shall not be used again to declare another package within any compilation unit.
3. Compilation-unit scope namespace: Exists outside the module, macromodule, interface, package, program, and primitive constructs. It merges the definitions of the functions, tasks, parameters, named events, net declarations, variable declarations and user defined types within the compilation-unit scope.
4. Text macro namespace: Is global within the compilation unit. Since text macro names are introduced and used with a leading ‘ character, they remain unambiguous with any other namespace. The text macronames are defined in the linear order of appearance in the set of input files that make up the compilation unit.
5. Module namespace: Merges the definition of modules, macromodules, interfaces, programs, functions, tasks, named blocks, instance names, parameters, named events, net declarations, variable declarations and user defined types within the enclosing construct.
6. Block namespace: Merges the definitions of the named blocks, functions, tasks, parameters, named events, variable type of declaration and user defined types within the enclosing construct.
7. Port namespace: Provides a means of structurally defining connections between two objects that are in two different namespaces.
8. Attribute namespace: Is enclosed by the (* and *) constructs attached to a language element. An attribute name can be defined and used only in the attribute namespace. Any other type of name cannot be defined in this namespace.

Listing the SystemVerilog supported and non-supported keywords:

• Keywords Supported in SystemVerilog
  

  implements	interconnect
  nettype	soft

• Keywords Not Allowed as SystemVerilog Identifiers
  

  accept_on	alias	always
  always_comb	always_ff	always_latch
  and	assert	assign
  assume	automatic	before
  begin	bind	bins
  binsof	bit	break
  buf	bufif0	bufif1
  byte	case	casex
  casez	cell	chandle
  class	clocking	cmos
  config	const	constraint
  context	continue	cover
  covergroup	coverpoint	cross*
  deassign	default	defparam
  design	disable	dist
  do	edge	else
  end	endcase	endchecker
  endclass	endclocking	endconfig
  endfunction	endgenerate	endgroup
  endinterface	endmodule	endpackage
  endprimitive	endprogram	endproperty
  endspecify	endsequence	endtable
  endtask	enum	event
  expect	export	extends
  extern	implies	final
  first_match	for	force
  foreach	forever	fork
  forkjoin	function	generate
  genvar	highz0	highz1
  if	iff	ifnone
  ignore_bins	illegal_bins	import
  incdir	include	initial
  inout	input	inside
  instance	int	integer
  interface	intersect	join
  join_any	join_none	large
  liblist	library	local
  localparam	logic	longint
  macromodule	matches	medium
  modport	module	nand
  negedge	new	nmos
  nor	noshowcancelled	not
  notif0	notif1	null
  or	output	package
  packed	parameter	pmos
  posedge	primitive	priority
  program	property	protected
  pull0	pull1	pulldown
  pullup	pulsestyle_onevent	pulsestyle_ondetect
  pure	rand	randc
  randcase	randsequence	rcmos
  real	realtime	ref
  reg	release	repeat
  return	rnmos	rpmos
  rtran	rtranif0	rtranif1
  scalared	sequence	shortint
  shortreal	showcancelled	signed
  small	solve	specify
  specparam	static	string
  strong0	strong1	struct
  super	supply0	supply1
  table	tagged	task
  this	throughout	time
  timeprecision	timeunit	tran
  tranif0	tranif1	tri
  tri0	tri1	triand
  trior	trireg	type
  typedef	union	unique
  unsigned	use	var
  vectored	virtual	void
  wait	wait_order	wand
  weak0	weak1	while
  wildcard	wire	with
  within	wor	xnor
  xor

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

ALT_NMP Namespace

The ALT_NMP namespace is an alternative method for name-space mapping in a mixed VHDL and Verilog environment. It deals with inconsistencies between the VHDL and Verilog namespaces.

The ALT_NMP namespace is set with the following environment variable:

CDS_ALT_NMP = MATCH

In the ALT_NMP namespace, you cannot have two names that vary only in case. For example, do not name a library MyLib when you already have a library mylib.

The ALT_NMP namespace has the following name mapping rules:

• When case-sensitive and case-insensitive namespaces interact, the case-sensitive namespace is treated as case-insensitive. However, escaped names from the case-insensitive namespace are not changed. The mapping of escaped names in this case is irreversible. For example, \AbC\ in the VHDL namespace is irreversibly mapped to AbC in the Verilog namespace.
• When names in case-insensitive namespaces are mapped to the LibraryUnix namespace, they are treated as lower case. When names in case-sensitive namespaces are mapped to the LibraryUnix namespace, they are not changed.

You might face case-sensitive issues while compiling the VHDL-AMS entities, to resolve these issues, see Advice and Solutions for VHDL-AMS Compiler Issues.

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

CDBA Namespace

CDBA normal identifiers are case-sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

All alphanumeric characters and symbols are allowed in CDBA normal identifiers except the comma ( , ), backslash ( \ ), forward slash ( / ), and the opening ( < ) and closing angle brackets ( > ). Spaces are not allowed. Opening and closing parentheses are allowed with an identifier only if they enclose digits.

CDBAFlat Namespace

The CDBAFlat namespace is used by applications. CDBAFlat is identical to the CDBA namespace except for the following:

• The pipe character ( | ) is used as the hierarchy delimiter character instead of the forward slash character ( / )
• Bus bit characters are enclosed in parentheses ( () ) instead of angle brackets ( < > )

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Concept Namespace

The Concept namespace has many similarities to the VHDL namespace. It has both a normal and an escaped form. The normal form is case insensitive; the escaped form is used only to provide case sensitivity. The escaped form starts and ends with a backslash ( \ ), and double backslashes ( \\ ) can be used to include a backslash in the identifier. Escaped identifiers and normal identifiers that are otherwise identical denote different objects.

The normal form also allows quoting. You can use either a quotation mark ( " ) or an apostrophe ( ' ), and you can start the quoting anywhere in the identifier. You must match an opening quotation mark or apostrophe with a closing one of the same type (" or '). You can use a quotation mark to include an apostrophe, and use an apostrophe as part of the identifier. Hence "ab'cd" and 'ab''cd' are equivalent identifiers that contain an apostrophe.

The Concept namespace has no keywords. Spaces are allowed except at the beginning and ends of a normal identifier.

All printable ASCII characters might be used in a normal identifier except for the apostrophe ( ' ), the quotation mark ( " ), the angle bracket ( < ) and the colon ( : ). These four characters can be used in quoted names where the quotation mark is different from the included quotation mark or else where the included apostrophe is doubled. Spaces can also be used if they are not the first or last character. If quoted, this means the first or last character other than the quotation mark.

Escaped identifiers can contain any of the above characters (all printable graphic ASCII characters). Only the backslash ( \ ) needs to be doubled to be included. Blank spaces are legal anywhere in an escaped name.

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

GCF Namespace

The General Constraint Format (GCF) namespace is case sensitive. Names cannot be longer than 1024 characters.

GCF Normal Names

GCF normal names can contain only alphanumeric characters (a-z, A-Z, 0-9) and the underscore character (_). In addition, the following special characters are allowed if they are specified as delimiters in the header section of the GCF file:

• The hierarchy divider character
  If the hierarchy divider character is not defined in the header section of the GCF file, the default hierarchy divider is the period (.).
• The bus bit index characters—usually the left and right square brackets, parentheses, or angle brackets ([] () <>). The index characters can enclose one positive integer to represent a single object, a pair of positive integers separated by a colon to represent a range, or an asterisk to represent all objects in the array. For example: pipe[4], pipe[1:3], or pipe[*]
  If the bus bit index characters are not specified in the header section of the GCF file, the default index characters are the left and right angle brackets (<>).

Normal names cannot include any other characters unless they are escaped. White space characters, such as tabs, spaces, or newlines are not allowed.

GCF Escaped Names

You can use characters that are not allowed in GCF normal names by escaping them. A character is escaped when it is preceded by a backslash character (\).

The following characters can be used in GCF names if they are escaped:

! “ # $ % & ‘ ( ) * + , - . / : ; < = > ? @ [ \ ] ^ ‘ { | } ~

The following examples show how escaped characters can be used in GCF names:

AMUX\+BMUX

pipe4\-done\&enb[3]

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Genesis Namespace

The Genesis namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

Genesis Normal Names

Genesis normal names can contain any printable ASCII characters—which include alphanumeric characters (a-z, A-Z, 0-9), the underscore character (_), and control characters— except the following special characters:

|   Hierarchy delimiter character

[ ]   Bus bit characters

Genesis Escaped Names

You can use characters that are not allowed in Genesis normal names by escaping them. A character is escaped when it is preceded by a backslash character (\).

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

LEF and DEF Namespaces

The Library Exchange Format (LEF) and Design Exchange Format (DEF) namespaces are case sensitive.

LEF and DEF Normal Names

LEF and DEF names can contain any ASCII characters except the semicolon (;), pound sign (#), newline (\n), or space characters.

In addition, the following special characters can be used in LEF and DEF names:

• Characters that denote regular expressions:
  * Matches any sequence of characters
  – Matches any sequence of characters up to the next period (.)
  % Matches a single character
• Bus bit index characters, as defined in the BUSBITCHARS statement
  The default index characters are the left and right square brackets ([]).
• Hierarchy divider character, as defined in the DIVIDERCHAR statement
  The default hierarchy divider character is the forward slash (/).

LEF and DEF Escaped Names

You can use characters that are not allowed in LEF and DEF normal names by escaping them. A character is escaped when it is preceded by a backslash character (\).

Reserved LEF Keywords

The following keywords are reserved in the LEF namespace and cannot be used as LEF identifiers.

abut	abutment	accurrentdensity
active	analog	and
antennaareafactor	antennalengthfactor	antennametalarea
antennametallength	antennasize	anyedge
array	average	beginext
block	bottomleft	bottomright
buffer	busbitchars	by
cannotoccupy	canplace	capacitance
capmultiplier	class	clock
clocktype	columnmajor	componentpin
components	core	corner
correctionfactor	correctiontable	cover
cpersqdist current	currentden	currentsource
cut	cutarea	data
database	dccurrentdensity	default
defaultcap	delay	dielectric
direction	dividerchar	do
edgecapacitance	edgerate	edgeratescalefactor
edgeratethreshold1	edgeratethreshold2	eeq
else	end	endcap
endext	extension	fall
fallcs	fallrs	fallsatcur
fallsatt1	fallslewlimit	fallt0
fallthresh	fallvoltagethreshold	false
fe	feedthru	fixed
floorplan	fn	foreign
frequency	frompin	fs
function	fw	gcellgrid
generate	generator	ground
height	history	hold
horizontal	if	inout
inoutpinantennasize	input	inputnoisemargin
inputpinantennasize	integer	intrinsic
invert	inverter	irdrop
iterate	iv_tables	layer
leakage	lengththreshold	leq
library	macro	masterslice
match	maxdelay	maxload
megahertz	metaloverhang	milliamps
milliwatts	minfeature	minpins
mpwh	mpwl	mustjoin
mx	mxr90	my
myr90	namemapstring	namescasesensitive
nanoseconds	negedge	nets
new	noisetable	nondefaultrule
noninvert	nonunate	nowireextensionatpin
obs	off	offset
ohms	on	or
orientation	origin	output
outputnoisemargin	outputpinantennasize	outputresistance
outputresistance	overhang	overlap
overlaps	pad	path
pattern	peak	period
picofarads	pin	pitch
placed	polygon	port
posedge	post	power
pre	property	propertydefinitions
pulldownres	pwl	r0
r180	r270	r90
range	real	recovery
rect	resistance	resistive
ring	rise	risecs
risers	risesatcur	risesatt1
riseslewlimit	riset0	risethresh
risevoltagethreshold	rms	routing
rowmajor	rpersq	samenet
scanuse	sdfcond	sdfcondend
sdfcondstart	setup	shape
shrinkage	signal	site
size	skew	source
spacer	spacing	specialnets
stable	stack	start
step	stop	string
structure	symmetry	table
tableaxis	tabledimension	tabledimension
tableentries	taperrule	then
thickness	tiehigh	tielow
tieoffr	time	timing
to	topin	topleft
topofstackonly	topright	tracks
transitiontime	tristate	true
type	unateness	units
universalnoisemargin	use	uselengththreshold
user	variable	version
vertical	vhi	via
viarule	victimlength	victimnoise
virtual	vlo	voltage
volts	w	width
wirecap	wireextension	x
y

Reserved DEF Keywords

The following keywords are reserved in the DEF namespace and cannot be used as DEF identifiers.

align	array	assertions
beginext	bottomleft	busbitchars
by	cannotoccupy	canplace
capacitance	commonscanpins	component
componentpin	components	constraints
cover	defaultcap	design
diearea	diff	direction
distance	dividerchar	do
drivecell	e	eeqmaster
end	endext	equal
estcap	fall	fallmax
fallmin	fe	fixed
floating	floorplan	floorplanconstraints
fn	foreign	fromclockpin
fromcomppin	fromiopin	frompin
fs	fw	gcellgrid
generate	group	groups
history	holdfall	holdrise
horizontal	in	integer
iotimings	layer	max
maxdist	maxhalfperimeter	maxx
maxy	microns	min
minpins	mustjoin	n
namemapstring	namescasesensitive	net
nets	new	nondefaultrule
noshield	ordered	original
out	parallel	partitions
path	pattern	patternname
pin	pinproperties	pins
placed	property	propertydefinitions
range	real	rect
reentrantpaths	region	regions
rise	risemax	risemin
routed	row	rows
s	scanchains	setupfall
setuprise	shape	shield
shieldnet	site	slewrate
soft	source	spacing
special	specialnet	specialnets
start	step	stop
string	style	subnet
sum	synthesized	taper
taperrule	technology	timingdisables
toclockpin	tocomppin	toiopin
topin	topright	tracks
turnoff	units	unplaced
use	variable	version
vertical	vias	voltage
vpin	w	weight
width	wirecap	wiredlogic
xtalk

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Library Namespace

The name mapping software supports a Library namespace that maps to either the LibraryUnix or the LibraryNT namespace, depending on which operating system the software is running. For programs running on UNIX, it is the same as the LibraryUnix namespace. For programs running on Windows, it is the same as the LibraryNT namespace.

LibraryUnix Namespace

LibraryUnix is used for library names in cds.lib files. It is also used for cell and view directory names in libraries that are stored on UNIX systems. LibraryUnix is designed to follow the rules for creating directory names on UNIX systems, except that it is more restrictive. Many characters, such as the period ( . ) and the comma ( , ), which are legal in the file system, are not allowed in LibraryUnix.

LibraryUnix is a case-sensitive namespace; for example, the filenames abc and AbC refer to different directories.

All alphanumeric characters plus the underscore ( _ ), at sign ( @ ), and pound sign ( # ) are allowed in LibraryUnix identifiers.

LibraryNT Namespace

The LibraryNT namespace is used for cell and view subdirectories in Windows libraries. LibraryNT is a case-insensitive, but case-preserving, namespace. This means the filenames abc and AbC are the same file, and only one of them can exist in any given directory. Digits, the underscore character ( _ ), the at sign ( @ ), the percent sign ( % ), and the pound sign ( # ) are allowed. Several names are reserved by Windows. These might be thought of as keywords that are illegal names. The keywords are aux, con, com0 through com9, lpt0 through lpt9, nul, and prn.

LibraryNT uses the pound sign ( # ) followed by two hex digits to map characters that are otherwise illegal.

LibraryNT uses the percent sign ( % ) to map case-sensitive uppercase letters. An X in Verilog becomes %X in LibraryNT.

LibraryNT also uses the percent sign ( % ) to map names that would otherwise look like reserved names. For example, a cell named lpt4 in a UNIX library is called %%lpt4 in a Windows library.

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Print Namespace

The Print namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

Names in the Print namespace can contain any printable ASCII characters, which include alphanumeric characters (a-z, A-Z, 0-9) and control characters.

There is no escaping mechanism in the Print namespace.

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

SDF Namespace

The Standard Delay Format (SDF) namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

SDF names cannot be longer than 1024 characters.

SDF Normal Names

SDF normal names can contain only alphanumeric characters (a-z, A-Z, 0-9) and the underscore character (_). In addition, the following special characters are allowed:

• The hierarchy divider character
  If the hierarchy divider character is not specified in the header section of the SDF file, the default hierarchy divider is the forward slash (/).
• Bus bit index characters—square brackets that enclose a positive integer to represent a single object or a pair of positive integers separated by a colon to represent a range. For example: pipe4[3] or pipe4[0:2]. The default index characters are the left and right square brackets ([]).

SDF normal names cannot include any other characters unless they are escaped. White space characters, such as tabs, spaces, or newlines, are not allowed.

SDF Escaped Names

You can use characters that are not allowed in SDF normal names by escaping them. A character is escaped when it is preceded by a backslash character (\).

The following characters can be used in SDF names if they are escaped:

! “ # $ % & ‘ ( ) * + , - . / : ; < = > ? @ [ \ ] ^ ‘ { | } ~

The following examples show how escaped characters can be used in SDF names:

AMUX\+BMUX

pipe4\-done\&enb[3]

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

SPF Namespace

The Standard Parasitic Format (SPF) namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

SPF Normal Names

SPF normal names can contain any ASCII character except white space characters such as space or tab. The following special characters are allowed:

• The hierarchy divider character, as defined in the header section of the SPF file. If the hierarchy divider character is not defined, the default hierarchy divider is the forward slash (/).
• Bus bit index characters, as defined in the header section of the SPF file. The index characters can enclose only one positive integer; a range is not allowed. If the bus bit index characters are not defined in the header section of the SPF file, the default index characters are the left and right square brackets ([]).

SPF Escaped Names

You can use characters that are not allowed in SDF normal names by escaping them. A character is escaped when it is preceded by a backslash character (\).

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

SPEF Namespace

The Standard Parasitic Exchange Format (SPEF) namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

SPEF Normal Names

SPEF normal names can contain only alphanumeric characters (a-z, A-Z, 0-9) and the underscore character (_). In addition, the hierarchy divider character and the bus bit index characters are allowed. The default hierarchy divider character is the forward slash (/); the default index characters are the left and right square brackets ([]).

White space characters, such as space or tab, and control characters, such as newline, are not allowed.

SPEF Escaped Names

You can use characters that are not allowed in SPEF normal names by escaping them. A character is escaped when it is preceded by a backslash character (\).

The following characters can be used in SDF names if they are escaped:

! “ # $ % & ‘ ( ) * + , - . / : ; < = > ? @ [ \ ] ^ ‘ { | } ~

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Spectre Namespace

The Spectre namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

Spectre Normal Names

Spectre normal identifiers must be in one of the following forms:

• The identifier must begin with an alphabetical character (a–z, A–Z) or an underscore (_) and can only be followed by zero or more of the following characters: alphanumeric characters (a–z, A-Z, 0–9), the underscore character (_), and the exclamation mark (!).
  For example:

  abc8
  Abc!
  _ABC

• The identifier must begin with one or more digits (0–9), followed by one or more alphabetical or underscore characters (a–z, A–Z, _), followed by a digit, and end with zero or more alphanumeric, underscore, or exclamation characters (a–z, A–Z, 0–9, _, !).
  For example:

  1a2abc
  11a45
  1asdfasdf4
  6adfsa324!

• The identifier must consist of one or more digits (0-9).
  For example:

  1
  135

Spaces are not allowed in Spectre identifiers.

Spectre Escaped Names

Characters are escaped in the Spectre namespace if they are preceded by a backslash (\). For example, the escaped form of a>= is a\>\=

The following characters are allowed in Spectre identifiers if they are escaped:

- ! “ # $ % & ’ () * + , . / \ 0-9 : ; < > = ? @ A-Z a-z [ ] ^ _ ‘ { } | ~ 

The TAB character is also allowed if it is escaped.

The following examples show how escaped characters can be used in Spectre identifiers:

ab\@c
\@aBc
1\$2abc8
1\23
1\\2!

Reserved Spectre Keywords

The following keywords are reserved in the Spectre namespace and cannot be used as Spectre identifiers.

abs	acos	acosh	altergroup
asin	asinh	atan	atan2
atanh	ceil	correlate	cos
cosh	else	end	ends
exp	export	floor	for
function	global	hypot	ic
if	inline	int	library
local	log	log10	M_1_PI
M_2_PI	M_2_SQRTPI	M_DEGPERRAD	M_E
M_LN10	M_LN2	M_LOG10E	M_LOG2E
M_PI	M_PI_2	M_PI_4	M_SQRT1_2
M_SQRT2	M_TWO_PI	march	max
min	model	nodeset	P_C
P_CELSIUS0	P_EPS0	P_H	P_K
P_Q	P_U0	parameters	paramset
plot	pow	print	real
return	save	sens	sin
sinh	sqrt	statistics	subckt
tan	tanh	to	truncate
vary

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

SpectreHDL Namespace

The SpectreHDL namespace is case sensitive. This means that the identifier AbC and the identifier abc refer to two different objects.

SpectreHDL Normal Names

SpectreHDL normal identifiers can contain only alphabetical characters (a–z, A–Z), digits (0–9), and underscores (_). The identifiers must begin with an alphabetical character or an underscore.

SpectreHDL Escaped Names

Escaped identifiers in the SpectreHDL namespace must begin with a backslash character (\) and end with a space (space, tab, or newline character). Escaped names can contain any printable ASCII character.

Reserved SpectreHDL Keywords

The following keywords are reserved in the SpectreHDL namespace and cannot be used as SpectreHDL identifiers.

abs	abstol	ac_stim	acos
acosh	always	analog	analysis
ascii	asin	asinh	assert
assign	atan	atan2	atanh
bound_step	branch	break	break_point
build_string	build_table	bus	case
ceil	complex	const	continue
cos	cosh	cross	debug
default	do	domain	dot
else	enum	error	event
exclude	exp	export	fatal
fclose	fdebug	fflush	final
finish	flicker_noise	floor	flow
fopen	for	fread	fread_table
freq	from	fstrobe	fwrite
fwrite_table	generate	global	halt
hypot	idtmod	if	inf
initial	inout	input	integ
integer	interpolate	laplace_nd	laplace_np
laplace_zd	laplace_zp	last_crossing	limexp
ln	log	mag	max
min	model	module	negedge
net	netlist_node_alias	node	noise_table
notice	output	param_given	parameter
pclose	phase	popen	posedge
pow	pwl	pwr	quantity
random	read	real	reg
reject_step	reltol	return	sin
sinh	slew	sqrt	state
step	stop	str	strcat
strchr	strcmp	strcpy	strcspn
stream	string	strlen	strobe
strrchr	strspn	strstr	strtoint
strtoreal	substr	switch	system
table	tan	tanh	tdelay
temp	terminal	threshold	time
transition	unit	val	void
vt	wait	warning	when
while	white_noise	wire	write
zdelay	zi_nd	zi_np	zi_zd
zi_zp

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Spice Namespace

The Spice namespace is case insensitive. This means that the identifier AbC and the identifier abc refer to the same object.

Spice Normal Names

Spice identifiers must begin with an alphabetical character. Identifiers can contain alphabetical characters (a–z, A–Z), digits (0–9), and the following characters: # % * - < > [ ] _ $ ! + /

Spice Escaped Names

Any character that is preceded by a backslash (\) is escaped in the Spice namespace.

Reserved Spice Keywords

The following keywords are reserved in the Spice namespace and cannot be used as Spice identifiers.

ac	aci	agauss	all
am	at	aunif	avg
bart	beta	bisection	black
brief	cross	current	data
dc	debug	dec	deriv
derivative	dtemp	enddata	err1
exp	fall	fil	find
freelib	freq	from	fs
gauss	goal	hamm	hann
harris	ic	ignor	integ
integral	kaiser	lam	last
limit	lin	max	maxfld
mer	min	minval	model
monte	nodeset	none	norm
numf	oct	opt	optimize
par	passfail	pe	pl
plot	poi	power	pp
pu	pulse	pwl	r
rd	rect	results	rin
rise	rms	rout	sffm
sin	start	sweep	targ
td	temp	to	tol
top	trig	uic	unif
unorm	voltage	weight	when
yin	ymax	ymin	yout
zin	zout

Related Topics

Name Mapping SKILL Functions

Namespaces for Different Data Types

Name Mapping Rules

Return to top