There are important differences between CDL format and the OpenAccess Virtuoso-Schematic view. CDL Out generates a netlist hierarchy that duplicates the hierarchy of your design. Each cell in the schematic becomes a separate subcircuit in the netlist. The hierarchical netlister automatically prefixes each instance name with the proper character for its element type; for example, "M" for MOSFET and "R" for resistor. This minimizes mapping and name translation.
CDL Out names instances and nets differently than a flat netlister. A flat netlister maps all the names to unique names. This avoids naming conflicts if you use identical names for instances in different cells of your schematic.
How Illegal Names are Mapped during CDL Out?
How CDL Out Translates Parameters?
How are Inherited Connections Supported in CDL Out?
How CDL Out Translates Instances of Primitive Devices?
How CDL Out Translates Global Signals?
Which CDL Formats are Generated for Primitive Components?