From

Specifies the source file of the Verilog modules.

File

Specifies the path to the file.

Browse

Selects the files one at a time.

The Verilog file you select must have one of the following extensions: .vams or .v because most Cadence applications recognize only files with these extensions as Verilog files.

To

Specifies the destination files of the Verilog modules.

Library

Selects the library in which you want to place the cellviews when the Verilog file is compiled. The cellviews are present in the implicit temporary directory, not in the master library.

If the library is fixed by some other rules in the design data, you won’t be able to edit the Library field. For example, design data created by the Virtuoso schematic editor typically does not allow you to change the library.

View

Specifies a name for the Verilog view. You can choose any name; the default name is module.

The view gets implemented later with the modules in the Verilog file by other applications in the flow. For example, in the design preparation step, AMS creates cellviews for the modules in the implicit temporary directory.

Update library list

Adds the specified library to the inherited library list of the cell, instance, or occurrence. If you select this option, the library is added as the first library in the inherited library list.

If the library is already in the inherited library list, this field is grayed-out.

Update view list

Adds the specified views to the inherited view list for the cell, instance, or occurrence. If you select this option, the view is added as the first view in the inherited view list.

If the view is already in the inherited view list, this field is grayed-out.