Glossary
The below glossary defines the terms and concepts that you should understand to use Dracula effectively.
The process of replacing the net and device name information in the layout netlist with the corresponding net and device name information from the schematic netlist.
A pin geometry-only entity that represents layout data that does not exist or can be ignored.
Labels you can specify in a Dracula rules file via the *BREAK command. When PDRACULA processes a file containing these labels, it generates a jxrun.com script file that allows you to submit a run with a starting as well as an optional stopping point in the script file, based on these labels.
An acronym that stands for Circuit Description Language, which is a subset of the SPICE format that describes the device and block level connectivity.
A schematic or layout entity that contains leaf (device) or block (instances) data as well as interconnect data.
Boundary generated by Dracula that encompasses the data inside an Hcell.
Layout layer data used to create the canonical devices, such as nwell, pplus, nplus, poly, contact, metal1, and so on.
Hierarchical Dracula mode that verifies cells declared as HCELLs individually.
Errors reported from a Composite Mode Hierarchical Dracula run.
Hierarchical Dracula mode that verifies the rest of the flattened design not designated as HCELLs.
The process of combining two inputs together but do not merge them.
The file extension of the Dracula binary-generated data files.
Refers to the section of the Dracula rules file that specifies the administrative commands, which the tool uses for run, such as the layout format and names of input files.
Number of errors found during a Dracula LVS run.
A mismatch found during an LVS run, based on an unmatched net or device.
An acronym that stands for Design Rules Checker, which analyzes the layout data and flags any physical violations, such as spacing or enclosure, based on the commands in the DRC rules files.
An ASCII text file lists text strings and its (X,Y) coordinates with respect to the flattened layout on each line. Also, you can optionally specify which conductive layer the text attaches to. If you omit this information, Dracula attaches the text to the conductive layer in the layout, defined in the rules file that's underneath the specified coordinates. You can use this file to supplement layout texts or to supersede the existing layout text that exists at the specified coordinates.
An acronym that stands for Electrical Rules Checker, which performs electrical connectivity checks on a layout and flags any violations, based on the commands in the ERC rules file.
Graphic structure that contains Dracula generated error flags that are used to display a detected violation, which you can overlay on top of the layout to help locate and resolve these errors.
Data generated by Dracula representing a violation based on the commands in a Dracula rules file.
Process of generating a representation of a layout that contains the layout’s electrical functions rather than its physical description.
Expands the hierarchical layout or schematic data to one common plane.
A cell you either define or let the software automatically define for you based on certain criteria for a hierarchical run. Dracula verifies a cell defined as an HCELL only once during the run. An HCELL may contain devices only, instances of other cells, or a combination of both.
Is similar in structure to the edtext file, but used for supplementing or superseding the layout texts in HCELLs.
An exploratory problem-solving technique that utilizes the self-educating techniques to improve performance.
Verification that uses the nested structure of a layout database to perform designated operations on Hcells, the composite plane of the layout, as well as the Hcell-to-Hcell and Hcell-to-Composite interactions.
Initial Correspondence Node Pair
Corresponding texted nets with same names in the layout, and schematic used by Dracula LVS for device matching during the verification process.
Refers to the section of the Dracula rules file that specifies the layout layers, which you want Dracula to read in for the run.
Electrical net connections between the canonical devices.
Is the name of the PDRACULA-generated script file listing all modules called during a run, based on the commands in the rules file.
Words reserved by a program for special meanings, for example, commands, functions, or options.
Is a representation of a circuit in a geometric topological form; instead in a logical or an electrical form.
An operation that analyzes one or more inputs and generates an output based on a set of rules. Boolean (AND, OR, NOT, XOR).
Compiler that converts network descriptions or ASCII netlists into a binary file, LVSLOGIC.DAT, used as schematic input for LVS.
An acronym that stands for Layout Parameter Extraction, which extracts and computes the canonical and/or parasitic parameter values from the layout, and creates a CDL or SPICE compatible netlist.
An acronym that stands for Layout Versus Layout, which compares two layouts and reports only the electrical differences between the two. Note that LVL does not report graphical differences.
An acronym that stands for Layout Versus Schematic, which compares the devices and connectivity in the layout to the devices and connectivity in the corresponding schematic and reports discrepancies found in the layout.
A file that contains a series of commands, which the tool can run during the job.
Glass plate containing photographically produced images corresponding to patterns from layout data during fabrication.
Devices that correspond between the layout and schematic.
Unit of measurement equal to 1/1000 of a millimeter.
Unit of measurement equal to 1/1000 of an inch.
Representation of a specific device in the schematic or layout.
A wire in the schematic or shape in the layout that carries an electrical information.
An ASCII file that lists the components and the connections to them.
A set of non-adjacent facing edges or adjacent edges that create an external angle of less than 90 degrees.
A design that has an incomplete connection.
Refers to the section of the Dracula rules file that specifies the commands, which drives the tool to perform the desired DRC, ERC, or LVS functionality.
Shapes whose edges form internal right angles and are parallel to the X and Y axis, also known as "Manhattan Geometry".
Graphic structure that contains Dracula generated error flags that are used to display a detected violation, which you can overlay on top of the layout to help locate and resolve these errors.
Refers to a relatively large metallic area on the periphery of a chip to which I/O wires are attached. These are also called as “bonding pads”.
A value associated with a device, such as the width and length of a MOS gate.
The process of measuring and calculating parameter values associated with a device and adding them to an appropriate netlist for comparison during LVS.
Electrical properties (not elements) that add circuit characteristics to the layout not included in the schematic.
Phantom layout devices (such as capacitors or diodes) that are not part of the schematic but act like a canonical device, based on the topological relationship of conductive layers in the layout.
Dracula preprocessor that compiles and verifies the Dracula rules file, and creates the UNIX script files to perform the requested job.
Point on a device or cell in the layout or schematic where you can make an electrical connection.
An acronym that stands for Parasitic Resistors Extraction, which extracts the parasitic resistors formed by conductor layers, such as poly, metal, and so on, and computes their parameter values.
Top-level cell in the design’s layout.
Canonical device, for example, transistor, resistor, capacitor, diode, and so on in a schematic or layout.
Derived layer used as a contact by Dracula, but not digitized as a contact in the layout.
See definitions for "PDW", "PUP", "SDW", or "SUP".
An ASCII file that defines the commands used by Dracula to perform the requested functionality. A Dracula rules files includes three main parts: the Description block, the Input-Layer block, and the Operation block.
Proportion used in determining the relationship of a representation to that which it represents.
Is the drawing of the logical representation of an electronic design. The drawing includes symbols, pins, connecting lines, and paths to indicate connectivity. The drawing can also contain other graphics or text, such as sheet borders or notes that are not part of the connectivity data.
Is the factor of resistance for one square of a canonical or parasitic resistor device.
Is the process of reducing parallel or series devices to a single device.
Stands for Simulation Program with Integrated Circuit Emphasis; it is a general-purpose simulation netlist format used for IC checking.
The process of passing electrical information from one conductive layer to another by virtue of the fact that they touch without the use of a contact or via opening.
Is a material beneath the layout that encompasses all the layer data.
Default extension of the Dracula summary file.
Serial-up incomplete structure.
Serial-down incomplete structure.
Conductor layers used as connections to a device.
A switch that allows you to change between two states, for example, on or off.
A four-sided polygon constructed with two parallel sides.
Dracula file containing system and hierarchical information from your layout.
Any device or I/O, which does not match schematic to layout or vice-versa.
Simulated net connection in the layout.
The bounding box coordinates of the layout, which Dracula processes.
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