Product Documentation

Dracula Reference
Product Version IC23.1, September 2023

Contents

Preface

Related Documents

Typographic and Syntax Conventions

1

Overview

Introducing Dracula

Flat and Hierarchical Databases

Dracula Applications

Dracula Interfaces

Introducing Hierarchical Dracula

Hierarchical Structure

Functions Not Available in Hierarchical Rules Files

Hierarchical Dracula Modes

2

Using Dracula

Verifying a Design with Dracula

Creating a Rules File

Rules File Structure

Rules File Example

Compiling the Rules File

Running PDRACULA

Using PDRACULA Commands

Running Dracula

Interpreting Dracula Output

Dracula Distributed Processing

How Dracula Distributed Works

Setting Up for Dracula Distributed Processing

Creating a Node Configuration File

Running Dracula Distributed Processing

Distributed Dracula Files

Dracula Distributed Processing and the Dracula Graphical User Interface Tool

Dracula Distributed Processing in the Dracula 4.51 Release

Dracula Distributed Processing in the Dracula 4.6 release

Dracula Distributed Processing in the Dracula 4.7 release

Dracula Distributed Processing in the Dracula 4.8 release

Running Dracula in 32-bit or 64-bit Modes

3

Checking Design Rules (DRC)

Design Rules Checker

Conjunctive Rules

Description Block

Input-Layer Block

Operation Block

Executing DRC from a Design Rule Library

Developing and Executing a Design Rule

Viewing the Results

Viewing the Violations

Database Comparison

Hierarchical and Multilevel Hierarchical Design Rules Checker

Selecting HDRC Hcells

Creating Hcells, Hcell Environment, and Composite Plane

HDRC Error Reports

Sample HDRC Rules File

4

Checking Electrical Rules (ERC)

Electrical Rules Checker

Description Block

Input Layer Block

Operation Block

NMOS ERC Rules File

CMOS ERC Rules File

Hierarchical ERC

HERC Check Modes

HERC Limitations

5

Compiling Network Descriptions (LOGLVS)

Initial Correspondence Nodes

Preparing Netlists

LOGLVS Command Sequence

Control Commands

Expand or Flatten Commands

LOGLVS Examples

CDL Control Commands

SPICE and HSPICE Commands

.SUBCKT or .MACRO

.SWAP and Special Elements

Subcircuit Calls

CDL Element Definition

Capacitor Syntax

Resistor Syntax

Transistor (BJT) Syntax

Transistor (JFET) Syntax

Transistor (MOSFET) Syntax

CDL Macro Expansion

CDL File Example

Preparing Data Files

Preparing SPICE Files

Preparing Verilog Files

MOS_EXTENDED_REP

Shell Environment Variables Used By LOGLVS

Using Hierarchical LOGLVS

CDL and SPICE Formats

Hcell Definition Examples

LOGLVS Examples

6

Comparing Layouts and Schematics (LVS)

Layout Versus Layout

Schematic Versus Schematic

Hierarchical Layout Versus Schematic

Initial Correspondence Node Pairs

Trace and Discrepancy Points

Preparing for LVL

Running SVS in Flat Mode

Running SVS in Cell or Composite Mode

Running SVS in Hierarchical Mode

LVS Report Format

Sample LVS Report

Discrepancy Report Conventions

LVS Error Types

LVS Error Type 1

LVS Error Type 2

LVS Error Type 3

LVS Error Type 4

LVS Error Type 5

LVS Error Type 6

LVS Error Type 7

LVS Error Type 8

LVS Error Type 9

LVS Error Type 10

LVS Error Type 11

LVS Error Type 12

LVS Error Type 13

LVS Error Type 14

LVS Error Type 15

Device Recognition in LVS

Simple Parallel Pull-Up (PUP) Structure

Simple Series Pull-Up (SUP) Structure

Simple Parallel Pull-Down (PDW) Structure

Simple Series Pull-Down (SDW) Structure

Complex Gate Including PUPI, SUPI, PDWI, and SDWI

Simple Parallel Middle (PMID) Structure

Simple Series Middle (SMID) Structure

Undefined Elements

Isolating and Debugging Errors

Interpreting an LVS Discrepancy

Logical Equivalence in MOS Digital Circuits

Calculations on Parallel MOS Devices for LVS

W/L Calculation

W_eff MULDELW Calculation

MOS Devices Without Substrate Terminal

Calculations on Parallel and Series Resistor Devices width/length for LVS

Bipolar LVS Example

Hierarchical LVS

Basic Requirements

Selecting HLVS Hcells

Automatically Selecting HLVS Hcells

Hcell Text (Pin Names)

Masking Hcells with Black Boxes

Hcells and the BASE-LAYER

GEN-TEXT Commands

HLVS Error Types

Sample HLVS Input Rules File

Inherited Connections for LVS in Dracula Verification

7

Extracting Electrical Parameters (LPE)

LPE Flow Diagram

LPE Flow Diagram (continued)

Extracting SPICE Parameters

MOS Transistors

Parasitic Diode Parameters

Parasitic Capacitor Parameters

Element Resistor Parameters

Bipolar Transistor Area and Perimeter

Geometric Primitives

Reserved Parameter Keywords

User-Defined Parameters

Selective LPE Batch Example

Selective LPE Incremental Example

Features of the Example

Rules File in a MOS Example

NMOS LPE Input File

CMOS LPE Input File

Hierarchical LPE

8

Using Parametric Data (LPEPRO)

LPEPRO Overview

Terminal Commands

Administrative Commands

Network and Gate Commands

Delay Value Command

Path Analysis Commands

Report Commands

PRINT, TYPE, and STORE

Scanning Layout Parameters

Identifying Nodes in the Layout

CAPACITANCE Subcommand

DIODE Subcommand

PARAMETER Subcommand

SPICE Generator

Whole Chip or Whole Cell

Logic Gate Generator

Using the Logic Gate Generator

Wired-OR Examples

Calculating Delay

L/W Ratio, Capacitance, and Resistance

Using Delay Equation Options

Revising Schematic Data

Calculating Delays for Nonprimitive Gates

Reviewing Delay Information

9

Extracting Parasitic Resistance (PRE)

Overview of Parasitic Resistance Extraction

Second PRE Pass

Creating the Resistor and Resistor Terminal Layers

Using the CUT-TERM Command

Using a Command Sequence

Creating the Pad Terminal Layers

Error Conditions

Calculating Junction Resistance

Redistributing Parasitic Capacitances

Sample PRE Rules File

Considerations for Parasitic Resistance Extraction

Sample Data and Results

Hierarchical PRE

SPF File Overview

Dracula, CDC, DSPF and RSPF Flow

10

Using DRAC2CDL Netlist Generator

Running DRAC2CDL

Interactive Mode

11

Description Block Commands

ABORT-MULT-STAMP

ABORT-P-G-SHORT

ALLOW-RECONNECT

ANGLED-EDGE-TOL

BLOCK-NAME-ONLY

CARE-SPLIT-ORDER

CELL-CHILD-TEXT

CONN-INTER-WIRE

CONVERT-DATABASE

DRACBATCH-EMAIL

ENVIRONMENT-MAX

ERROR-PATH-WIDTH

EXPAND-GATE-DELI

EXPAND-INST-DELI

EXPAND-NODE-DELI

FILTER Commands

FIX-INPUT-ORDER

FLAG-ACUTEANGLE

FLG-EXPTH-OFFGRD

FLAG-PTH-OFFGRID

FLAG-SELFINTERS

GEN-TEXT-FLTNODE

HCELL-MAX-PLACEMENTS

HCELL-MAX-SEGMENTS

HCELL-OPTIMIZE-PLACEMENTS

INTERNODE-PREFIX

LAYER-FILE-TYPE

LIMIT-DRC-ERROR

M-Factor Commands

M-Factor Tolerance Commands

MATCH-P-G-BY-TYP

OUTPUT-ONE-LAYER

PREFIX-PARASITIC

REP-UNM-INST-PG

ROUND-OFF-TOLER

SCALE and REV-SCALE

SCALEOUT and REV-SCALEOUT

SIZE-MAX-VERTEX

SMASH-FLOAT-RES

SUB-PROGRAM-NAME

SYSTEM or SYSIN

UNSPEC-LAY-PARA

UNSPEC-SCH-PARA

ZERO-SPAC-F-EQU

12

Input-Layer Block Commands

CTEXT and ATTACH

FRAME-EXCLUDE-LAYER

FRAME-HOLE-LAYER

Layer Name Definition

OUT-ANNOTATED-LAYER

TEMPORARY-LAYER

13

Operation Block Commands

Logical Operations

Electrical Node Extraction

Sizing Operations

Circuit Element Extraction

Electrical Rule Checking

Layout Versus Schematic

Layout Parameter Extraction

ANGLED-EDGE-TOL

COEFFICIENT CAP

extractParasitic

GLOBAL-SCONNECT

A

Supported Database Records

B

Data Structure Translator

Running the Translator

C

Running Dracula

Running a Dracula DRC/ERC Job

Submitting the jxrun.com File

Running Other Dracula Programs

System Requirements

UNIX Case-Sensitivity Enhancements

Batch Job Queuing Utility

Glossary

Index

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