For an IC layout, you need to provide process setup information. When using the Clarity 3D Solver simulator, specify the process setup information in the .emproc files that are saved in a process corner directory, which is by default set to the .cadence/dfII/Sigrity/corners directory in the current working directory. When using EMX, specify the process setup information in the .proc files. The EM Solver assistant reads the directory and loads the process corner names in the Corner column of the Models section. The default process corner directory used by EMX is .cadence/dfII/Sigrity/corners.
When the layer stack information is available in an ICT or QRC technology file:
- Add a reference to the external ICT or QRC technology file along with the mapping information to map the external layers to Virtuoso layer.
- Provide details about substrates, height adjustment values for layers, values for dielectric simplification, and a list of layer-purpose pairs from which shapes are to be extracted.
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When the layer stack information is not available in an ICT or QRC technology file:
- Create a custom stackup with details about dielectric, metal, and via layers.
- Provide details about substrates, height adjustment values for layers, values for dielectric simplification, and a list of layer-purpose pairs from which shapes are to be extracted.
Related Topic: