Instance Terminals and Overriding Terminals

The "tieHigh", "tieLow", "tieOff", "power", "ground", and "signal" nets specified in verilog can be implemented in block domain using any physical-only net. An example for this is given below:

/ Verilog file for cell "top_level" view "layout"

// Language Version: 2001

module top_level (

A,

B,

C,

D,

Z

);

input A;

input B;

input C;

input D;

input _IN;

output Z;

output _OUT;

wire net1;

assign _OUT = 1’b1;

assign _IN = 1’b0;

block3 I1 ( .A(A), .B(B), .C(C), .Y(net1), .Z(1’b1));

block I2 ( .A(net1), .B(1’b1), .C(D), .Z(Z), .„nd! (1’b0), .\vdd! (1’b1));

endmodule // top_level

In the above example, observe the following in the connectivity:

• The terminals _IN and _OUT are connected to tie0 and tie1 nets, respectively.
• The instance terminals corresponding to I1/Z and I2/B are connected to tie.
• The instance terminals corresponding to I2/vdd! and I2/gnd! are connected to tie1 and tie0 nets, respectively

It is significant to understand that verilog designer has no clue how 1’b1 tieHi and 1’b0 tieLow nets will be implemented in the layout or block domain. It depends on the block designer to choose any physical only net to implement 1’b1 and 1’b0. For example, the following array of nets can be used to implement.

• _IN and I2/gnd! (tie0) to be implemented by net VSS (physical only).
• _OUT and I2/vdd! (tie1) to be implemented by net VDD (physical only).
• I1/Z and I2/B (tie1) to be implemented by net INTERNALVDD (physical only).

The following changes in the block domain must be made.

• Hide _IN _OUT terminals.
• Hide instance terminals I2/gnd!, I2/vdd!, I1/Z and I2/B.

Create overriding terminals and overriding instance terminals with same names to implement them using the above mentioned physical only nets.

Related Topics

Flows Supported by Abstract Generator

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