Congestion-Aware Pin Placement in Pin Optimizer
(Virtuoso Layout Suite EXL) By default, Pin Optimizer places pins considering DRC, minimum wire length, design constraints, and process rules, but does not consider routing information such as routing channel paths and congestion data. In certain designs, this might cause hot spots after pin optimization.
The following image shows the result of standard wire length-based pin optimization on a design.
After running global routing and congestion analysis on the design, the routing channel appears highly congested.
When pin placement becomes congestion aware, the routability of such designs improves.
The following example shows how congestion-aware pin optimizer helps with pin placement. Pin Optimizer internally uses the results from Global Router to find congestion-aware placement positions for pins and places the pins accordingly.
The following image shows the result of congestion analysis after running congestion-aware pin optimizer.
Running Pin Optimizer in the congestion-aware mode may result in an increase in total net length, which is expected because target pins might be placed further away. This is done to increase the routability of the design without increasing the design size or modifying the block locations.
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