Package files are important in SystemVerilog, SystemVerilog-AMS, VHDL, and VHDL-AMS for sharing and reusing common code definitions, such as functions or custom data types, between models. The Virtuoso HDL Package Setup form ensures that handling HDL package files becomes more intuitive, requires less maintenance, and improves the task flow for SystemVerilog, SystemVerilog-AMS, VHDL, and VHDL-AMS package files.
The following sections provide more details:
- How do I access the Virtuoso HDL Package Setup form?
- How do I enable the HDL Package Setup flow?
- How do I specify the directory to generate compilation results?
- How do I specify the compilation options?
- How do I define xrunArgs files?
- How do I ensure that the minimum number of libraries is used?
- How do I customize the form for hdl.var legacy?
- How do I avoid errors while using the HDL Package Setup form?
- How do I define the local package setup?
- How do I clean the compilation results?
- How do I check or view the compiled packages and their dependencies?
- How do I initialize the HDL Package Setup form using .cdsinit?
