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Netlist Generation and Customization
When the Simulation Environment (SE) netlists your design, it takes your design hierarchy (extracted schematic or layout) and the simulator primitive component library and generates a network description containing all instances, nets, and models in an appropriate format for your simulator.
When you extract and save your schematic, the system takes the connectivity information from the drawing and saves it to the disk. The netlister uses this data, the simulation data in the Cadence basic and sample libraries, and the modeling data to create the netlist for simulation.
The traversal method used in the design hierarchy to produce the netlist and the netlist syntax depends on your simulator choice. Consider that you want the netlist for a Verilog simulation to be at the logic gate level because Verilog can simulate primitives such as AND gates and AOIs. Additionally, you want the netlist for a SPICE simulation of the same design to be at the transistor level because SPICE cannot simulate logic gates.
Some Cadence netlisters flatten the hierarchy and produce an expanded description of the design. For HSPICE, the netlister can create either a flattened or a hierarchical netlist. The Verilog-XL netlister produces only a hierarchical netlist.
Related Topics
Netlist Customization With the .simrc File
Variables for Incremental Netlisting
Customization of Scale Factors
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