Product Documentation
Spectre Circuit Simulator and Accelerated Parallel Simulator RF Analysis in ADE Explorer User Guide
Product Version 23.1, June 2023

11

Top-down RF Design Methodology

This section describes a methodology for designing analog RF subsystems that fit into larger DSP systems. In particular, this section describes how to use a canonical set of top-down behavioral baseband models for exploring RF architectures in the analog design environment. These models come from the following categories in rfLib

These models provide RF designers with a fast method to map RF system specifications into detailed RF designs. The baseband models facilitate fast evaluation of candidate RF architectures specified with DSP metrics. The passband views of the baseband models provide a behavioral system testbench for checking detailed designs of individual RF system components.

Baseband models are behavioral models and all behavioral models sacrifice some accuracy for increased simulation speed. Such sacrifices are usually acceptable in architectural studies because many implementation-dependent details do not affect high level decisions. The modeling approach taken in top-down design is to simulate only those effects that drive the decisions at hand.

Baseband modeling in no way replaces passband modeling. Some effects missed by equivalent baseband models can affect high level decisions. However, the application of baseband models early and passband models later minimizes the number of slow simulations needed at the lower levels of design abstraction. Baseband models help you to quickly weed out designs that would surely fail tests simulated with passband models.

The success of a modeling approach to top-down design hinges on knowing how the models fit into the design flow and knowing exactly what each modeling parameter means. This chapter has two goals:

Top-Down Design of RF Systems

Ideally, the digital signal processing, or DSP, team specifies an RF subsystem that fits snugly into the DSP system. A snug fit means that

In a top down design flow like the one shown in Figure 11-1, the DSP team writes a functional specification for an RF subsystem that has not yet been designed. The functional specification describes what the RF subsystem should and should not do without describing how to build the RF subsystem.

The functional specification supplied by the DSP team describes the RF subsystem at the highest possible level of abstraction. At this point behavioral models can be specified rather than measured. This early in the design cycle, the functional specification might well be incomplete or inconsistent. A good top-down design flow can detect problems, such as omissions and inconsistencies in the design, early in the design cycle when they are easier and less expensive to fix. Problems detected later in the design cycle can be much more costly and very difficult to resolve.

Using the functional specification supplied by the DSP team and the behavioral baseband models from rfLib, the RF system designers can easily explore RF architectures in the analog design environment. The baseband models facilitate fast evaluation of candidate RF architectures specified with DSP metrics. By switching to the passband views of the baseband models, the RF design team maps DSP measurements to RF measurements. The passband views of the baseband models provide a behavioral system testbench for checking detailed designs for individual system components.

Using the functional specification and exploring and testing with the baseband and passband models, the RF team can efficiently create a detailed design specification that fully describes the RF subsystem. The design specification can include detailed instructions for building the RF subsystem. At this stage of the design cycle, everything that is known about the design is described at the lowest level of abstraction.

You can now extract behavioral models of a detailed design from simulated measurements. The problem remains that detailed designs usually do not exist until the project is complete. To jump directly to a detailed design implies that the design flow is bottom up. Bottom up flows are important in many projects, but not in all.

DSP and RF designers sometimes have trouble communicating through specifications because the two groups deal with different metrics. For example, DSP designers deal with bit error rates and error vector magnitude statistics whereas RF designers deal with intercept points and noise figures.

The new models described here are designed to help RF system designers in two ways.

Use Model for Top Down Design

The following steps outline the RF design process with focus on the early phases of the design as illustrated in Figure 11-1.

Figure 11-1 The Top Down Design Flow and Use Model

Specify the RF Subsystem in Terms of DSP Metrics

Before you begin the RF subsystem top-down design flow, the DSP design team should completely specify the RF subsystem in terms of DSP metrics. This preliminary step distinguishes the end of the DSP design flow from the beginning of the RF top down design flow and formally hands-off the RF subsystem design specifications to the RF design team.

Explore Candidate Architectures with Baseband Models

The first step in top down RF design is to select a candidate RF architecture. An RF architecture is a set of interconnected RF function blocks that, taken together, describe how a receiver or transmitter operates. You specify each function block in terms of standard RF metrics such as IP3, gain, bandwidth, and noise figure.

The models you use early in the design cycle as you explore candidate RF architectures must run fast. Each simulations can span hundreds of symbols and each symbol can easily span thousands of RF carrier cycles. The space defined by the function block specifications in each candidate architecture is far too vast to explore with slow, highly precise models. Models used for architectural exploration must quickly reduce the design space down to a size that can be explored with more precision.

The most efficient models for architectural exploration suppress the RF (IF) carrier and are called baseband models. In contrast, the passband models (introduced in the next step) do not suppress carriers.

You can use the Circuit Optimizer during architectural exploration to help balance the function block specifications for a candidate architecture. For example, you can use the Circuit Optimizer to minimize RMS EVM while ensuring that other measurements stay within acceptable limits.

When you have determined the nominal specifications for each function block, you must put tolerances around them. In the analog world specifications without tolerances are meaningless. The tolerance space is usually explored with some mix of experience, feasibility, a variety of analyses, and outright arbitrary decisions.

There are several ways that you can use the baseband models to test candidate tolerances as well as to determine some tolerances analytically.

One way to test a candidate set of tolerances is to run a Monte Carlo analysis on the metric of interest, like RMS, EVM, or signal-to-noise ratio (SNR).

Another approach is to use the Circuit Optimizer in reverse, as a de-optimizer, to determine worst case performance.

Yet another approach is to compute each tolerance separately from a parametric plot. When you have determined all but 2 or 3 tolerances, you can use a multidimensional parametric analysis to map out the performance space and easily identify the remaining tolerances.

Switch to Passband Models and Create an RF System Testbench

The second step in top down RF design is to create a passband view of the system model.

The passband system model performs two functions:

For computational efficiency during system passband testing, at any one time, model one or two selected function blocks at the device level. Model all other blocks in the system behaviorally using passband models.

Derive the tolerances by performing the same Monte Carlo analysis or Circuit Optimizer analysis you used to test the function block tolerances in the first step, but this time replace the DSP metrics with end-to-end RF metrics. After you know how far the end-to-end RF metrics can vary, you can insert a device-level model of a function block into the testbench to see how close it drives the system toward violating a derived end-to-end RF specification.

Implement the Function Blocks with Active and Passive Devices

The last step in the top down design process is to implement the function blocks with device models. Because the function blocks are specified in terms of standard RF metrics, you can easily measure the modeling parameters to make sure they fall within the specified tolerances. You can also insert the measured parameters back into the baseband model of the system to check the DSP metrics, or insert the device-level model directly into the passband testbench to check the derived end-to-end RF specifications.

Baseband Modeling

A baseband model for an RF function block simulates what happens to the baseband representation of a signal as it passes through the block. A baseband model maps input baseband signal trajectories into output baseband signal trajectories. If you sample a baseband signal periodically in time and plot the samples in the complex plane, the resulting scatter plot shows the symbol constellation.

Figure 11-2 mathematically defines a baseband representation of a passband signal. The i and q signals are the real and imaginary parts of a complex signal that rides on the two phases of an RF carrier.

Figure 11-2 Baseband Representation of a Passband Signal

Baseband models simulate only what happens to the carrier fundamental. Consequently, they only account for non-linearities with odd symmetry. Non-linearities with even symmetry produce no output at the carrier fundamental; they affect the carrier fundamental only when cascaded. For example, a second order non-linearity in one block can create a DC offset at it’s output. Upon passing through a subsequent block with another second order non-linearity, the DC offset can mix with the carrier to affect the output carrier fundamental. You should model cascaded blocks producing unfiltered even harmonics as a single baseband model rather than as separate baseband models cascaded together. The non-linearities that most often dominate performance have odd symmetry.

Example Comparing Baseband and Passband Models

The example in this section walks you through an Envelope analysis that illustrates the relationship between baseband and passband models. Following the simulation, you plot the baseband equivalent output signals as computed by the baseband and passband circuits.

The BB_test_bench schematic shown in Figure 11-3 illustrates the difference between passband and baseband modeling. This circuit is located in the rfExamples library.

Figure 11-3 The BB_test_bench Schematic

The BB_test_bench circuit shows a passband circuit (across the top of the schematic) and its baseband equivalent circuit (across the bottom of the schematic). The same baseband signals drive both circuits but only the passband circuit mixes the baseband signals up to RF. The power amplifier is not matched to either input or output impedances and both impedances are reactive.

Before you start, perform the setup procedures described in Chapter 3.

Opening the Baseband Test Bench Circuit

  1. In the CIW, choose File – Open.
    The Open File form appears.
  2. In the Open File form,
    1. Choose rfExamples in the Library Name cyclic field. (Choose the editable copy of rfExamples you created as described in Chapter 3.)
    2. Choose BB_test_bench in the Cell Names list box. Note that the View Name cyclic field displays Schematic.
    3. The completed Open File form appears like the one below.
  3. Click OK.
    The Schematic window for the BB_test_bench appears.
  4. In the Schematic window, choose Launch – ADE Explorer.
    The ADE Explorer opens.

Choosing Simulator Options

  1. Choose Setup – Simulator in ADE Explorer.
    The Choosing Simulator form appears.

  2. Choose spectre from the Simulator drop-down list.
  3. Click OK.
  4. [Optional] For remote simulation, choose Setup – Job Setup.
    The Job Policy Setup form appears.
    Choose Remote-Host for Distribution Method and specify the host machine and other options as needed.
  5. In the ADE window, choose Outputs – Save All.
    The Save Options form appears.
  6. In the Select signals to output (save) section, be sure allpub is highlighted.
  7. In the Save Options form, click OK.

Setting Up Model Libraries

  1. In ADE Explorer, choose Setup – Model Libraries.
    The Model Library Setup form appears.
  2. In the Model Library File field, type the full path to the model file including the file name, rfModels.scs.
  3. In the Model Library Setup form, click Add.
    The completed form appears like the one below.
  4. In the Model Library Setup form, click OK.
  5. In the ADE window, use Analyses - Disable to disable any analyses you ran previously. (Check the ADE window to verify whether or not an analysis is enabled.)

Setting Up the Envelope Analysis

  1. Choose Analyses – Choose in ADE Explorer.
    The Choosing Analyses form appears.
  2. In the Choosing Analyses form, click envlp.
    1. Choose Shooting for Engine.
    2. Enter 10u in the Stop Time field.
    3. Enter ff in the Clock Name field.
    4. Enter 1 in the Number of harmonics field.
    5. [Optional] Specify a Step Period.
      Step period is the time interval, in seconds, between points in the modulation file.
    6. Select moderate for Accuracy Defaults.

    The correctly filled out form appears below.
  3. In the Choosing Analyses form, click OK.

Running the Simulation

  1. In the ADE window, choose Simulation – Netlist and Run.
    The output log file appears and displays information about the simulation as it runs.
    Look in the CIW for a message that says the simulation completed successfully.

Plotting the Baseband Equivalent Output Signals

  1. In the ADE window, choose Results-Direct Plot-Main Form.
    The Direct Plot Form appears.
  2. In the Direct Plot Form, do the following:
    1. Select Replace for Plotting Mode.
    2. Select envlp for Analysis.
    3. Select Voltage for Function.
    4. Select time for Sweep.
      The Net selection appears in the Select cyclic field and the label Description: Envelope Voltage vs Time appears.
    5. Following the message at the bottom of the Direct Plot form
      Select Net on schematic...
      Click the baseband_I_out net.
    The first trace appears in the waveform window.
  3. In the Direct Plot Form, do the following:
    1. Select Append for Plotting Mode.
    2. Leave Voltage set for Function and time set for Sweep.
    3. Following the message at the bottom of the Direct Plot form
      Select Net on schematic...
      Click the baseband_Q_out net.
      The second trace is added to the waveform window. Both baseband equivalent output signals for the baseband model are plotted.
  4. In the Direct Plot Form, do the following:
    1. Leave Append for Plotting Mode and Voltage for Function.
    2. Select harmonic time for Sweep.
    3. Select Real for Modifier.
    4. Following the message at the bottom of the form,
      Select Harmonic Number on this form...
      Select 1 for harmonic number.
    5. Following the next message at the bottom of the form
      Select Net on schematic...
    Click the RF_out net.
    A third trace is added to the waveform window.
  5. In the Direct Plot Form, do the following:
    1. Leave Append for Plot Mode, Voltage for Function, harmonic time for Sweep, and 1 for Harmonic Number.
    2. Select Imaginary for Modifier.
  6. Following the message at the bottom of the form
    Select Net on schematic...
    Click the RF_out net again.
    A fourth trace is added to the waveform window. Both baseband equivalent output signals for the passband model are added to the plot.

In the waveform display window you should now see what at first appears to be two traces. When you look more closely, you should see that each trace is actually two traces, one nearly on top of the other, making a total of four traces.

The plot resulting from this example illustrates how well baseband modeling corresponds to the time-varying fundamental Fourier component computed by Envelope analysis and raises two questions:

Running a transient analysis with only the baseband models answers the first question. If from the ADE window you deactivate the passband circuit by setting the carrier_pb variable to zero, disable the Envelope analysis, and set up and run a 10μs transient analysis, you observe the same baseband results, but the transient simulation runs over 100 times faster.

Examining the Envelope results answers the second question. If you look closely at both waveforms you notice that the baseband waveforms clip at a slightly lower level than the Envelope waveforms. This is because hard limiting of the carrier generates higher-than-third-order harmonics and the behavioral baseband model only simulates third order non-linearities.

rfLib Library Overview

The rfLib include three kinds of models to support baseband modeling:

The instrumentation models provide stimuli, diagnostics, and performance metrics relevant to the DSP system.

Both the linear models with memory and the non-linear memoryless models simulate the function blocks in an RF architecture and are specified in terms of common RF metrics. The RF function block models include input referenced white Gaussian noise as specified by noise figure. The rfLib includes models for the following RF function blocks—amplifiers, mixers, filters, and phase shifters; where filters includes single resistors, capacitors, and inductors.

The non-linear models simulate AM/AM conversion [1] with a third-order polynomial that saturates at the peak of the transfer curve. The polynomial is specified by the gain and either the input-referred IP3 or the output-referred 1 dB compression point. Only the non-linear baseband models simulate AM/PM conversion. AM/PM conversion [1] is an important effect that is hard, if not impossible, to simulate with passband behavioral models. Figure 11-4 shows the basic baseband non-linearity.

Figure 11-4 Basic, Baseband Non-Linearity

The linear models are the key to simulating loading effects at baseband. In RF integrated circuits, loading effects are important because it is often hard to integrate impedance matching networks. The baseband models of reactive elements differentiate our approach from the spreadsheet-based approaches to RF system design. The baseband capacitor and inductor models (cap_BB and ind_BB in top_dwnBB) let you simulate reactive loading effects in the time domain, where non-linearities are more naturally modeled.

The baseband models of reactive elements also play a key role in modeling filters. Most digital communications text books [1,2] explain that you can model a passband transfer function at baseband by simply frequency-shifting the transfer function. What these books do not describe is how to implement the resulting transfer function in a general circuit simulator such as Spectre® circuit simulator RF analysis (SpectreRF). The shifted transfer function usually lacks complex conjugate symmetry about zero frequency and therefore has a complex impulse response.

The first consequence of modeling RF function blocks at baseband is that all equivalent baseband models have four terminals instead of two:

The mathematics illustrated in Figure 11-5 and Figure 11-6 summarize the ideas behind a time-varying coordinate transformation that models reactive elements at baseband. The mathematics apply to capacitors as well as inductors.

There is a well-documented but little-known electro-mechanical analogy for the derivation of the inductor baseband equivalent model. The four inductor terminals resemble the stator windings of a two-phase rotating machine with shaft speed equal to the RF carrier frequency. Modulation is mathematically analogous to the flux linking a stator winding due to currents in orthogonal rotor windings. The flux depends on the shaft angle just as a modulated signal depends on the carrier phase. Transforming the vectorial equation for v=Ldi/dt to the rotor reference frame suppresses the RF carrier and introduces a speed voltage [3,4,5,6,7,8,9], or back electro-motive force (back EMF), that couples the differential equations.

An expression for the real current (i.e. the passband current) appears in Figure 11-6. The real current is modeled as the projection of a two-dimensional rotating vector onto a stationary axis, the real axis. The vector rotates with an angular velocity equal to the RF carrier frequency.

Figure 11-5 Passband Current for an Inductor

The rotating vector also has a projection onto another stationary axis orthogonal to the real axis. In the baseband literature, the orthogonal projection is the Hilbert transform of the real signal. The constitutive relationship of the inductor, v=Ldi/dt, is expressed in terms of coordinates in a reference frame that rotates with the vector.

Figure 11-6 shows the constitutive inductor relationship between voltage and current in the rotating reference frame. Note that the trigonometric terms, the terms that slow simulation speed, are gone and the two projections are now coupled through speed voltages. The term speed voltage comes from the fact that the voltages depend on the angular speed of the rotating reference frame. In motor theory, that speed is the shaft speed. Speed voltage is similar to the back EMF in a motor. Because of speed voltages, baseband models of filters and reactive elements must have their carrier frequency specified. The carrier frequency is the frequency for which the baseband signals are referenced. For example, the carrier frequency for an RF filter would be the RF frequency while the carrier frequency for an IF filter would be the IF frequency.

Figure 11-6 Relationship Between Voltage and Current for an Inductor

The baseband counterparts of the passband filter models are built up from inductors and capacitors modeled in the rotating reference frame.

In the complex expression for v=Ldi/dt, if you replace d/dt with jω, you find that the impedance of the inductor changes from jLω to jL(ω+ωrf). The same holds for capacitors, which means a filter transfer function, H(ω), has a baseband equivalent equal to H(ω+ωrf). This is simply the original passband transfer function shifted to the left by an amount equal to the carrier frequency. Our time domain baseband models are consistent with the text book frequency domain explanation of baseband modeling.

Use Model and Design Example

This section describes how to use the baseband models during the architectural design phase. The following examples show you how to

The design goals were chosen arbitrarily. The example is meant simply to illustrate how to use the library and is a derivative of the design found in [10]. If you find that some parameters are not specified, leave them as default values. You construct the receiver from left to right, from input to output.

Opening a New Schematic Window

  1. In the CIW, choose File – New – Cellview.
    The New File form appears.
  2. In the Create New File form,
    1. Choose my_rfExamples in the Library Name cyclic field. (Choose the editable copy of rfExamples you created as described in Chapter 3.)
    2. Enter receiver_example in the Cell Name field.
    3. Select Composer-Schematic in the Tool cyclic field. schematic appears in the View Name field.
    4. The completed form appears like the one below.
  3. Click OK.
    An empty Schematic window for the receiver_example appears.

Opening the Analog Environment

  1. In the Schematic window, choose Launch – ADE Explorer.
    The ADE Explorer window opens.
  2. Set the simulator options from the Simulator window as described in “Choosing Simulator Options”.
  3. Set up the model libraries from the Simulator window as described in “Setting Up Model Libraries”.

Constructing the Baseband Model for the Receiver

Construct the receiver in the Schematic window by adding blocks from left to right, from input to output, as listed in Table 11-1.

Except for the resistor, ground, and port models (which come from the analogLib), all blocks come from the rfLib. Unless otherwise instructed, leave the port resistances at their default value of 50 Ohms.

Table 11-1 Blocks Used to Create the Receiver
Block Name and Reference Element Name Library and Category

CDMA signal source — See Adding the CDMA Signal Source

CDMA_reverse_xmit

From the measurement category in rfLib.

Resistor—attach to CDMA signal source

res

From analogLib

Driver — See Adding the Driver

BB_driver

From the measurement category in rfLib.

Low noise amplifier — See Adding the Low Noise Amplifier

LNA_BB

From the top_dwnBB category in rfLib.

Butterworth bandpass filter — See Adding a Butterworth Band Pass Filter

BB_butterworth_bp

From the top_dwnBB category in rfLib

RF-to-IF mixer — See Adding an RF-to-IF Mixer

dwn_cnvrt

From the top_dwnBB category in rfLib

Butterworth bandpass filter — See Adding Another Butterworth Bandpass Filter

BB_butterworth_bp

From the top_dwnBB category in rfLib

IQ demodulator — See Adding an IQ Demodulator

IQ_demod_BB

From the top_dwnBB category in rfLib

Butterworth lowpass filters (create two) — See Adding Two Butterworth Lowpass Filters

butterworth_lp

From the top_dwnPB category in rfLib

Instrumentation model — See Adding an Instrumentation Block

offset_comms_instr

From the measurement category in rfLib.

Terminator — See Adding an Instrumentation Terminator

instr_term

From the measurement category in rfLib

Grounds—attach to RF-to-IF mixer, IQ demodulator, and Instrumentation model

gnd

From analogLib

Adding the CDMA Signal Source

Add the first receiver block, a CDMA signal source (CDMA_reverse_xmit), to the schematic.

  1. In the Schematic window, choose Create – Instance.
    The Add Instance form appears. It may be empty or it may display information for a previously added element. The default for the View field is symbol.
  2. In the Add Instance form, click Browse.
    The Library Browser - Add Instance form appears.
  3. In the Library Browser - Add Instance form,
    1. If necessary, click Show Categories to display the Category column so you can view the elements (or cells) in the rfLib by category.
    2. In the Libraries column, click rfLib to display categories of elements in rfLib.
      The Everything category is displayed by default and all cells in rfLib are listed in the Cells column. (In the Add Instance form, rfLib displays in the Library field.)
    3. In the Category column, click measurement to list only the cells in the measurement category.
    4. In the Cell column, click CDMA_reverse_xmit.

    In the Library Browser, cell CDMA_reverse_xmit and it’s default view symbol are both selected.
    In the Add Instance form,
    • rfLib appears in the Library field
    • CDMA_reverse_xmit displays in the Cell field
    • symbol displays in the View field

    The CDF parameters for the element and their default values appear at the bottom of the form.
  4. To place a CDMA_reverse_xmit block in the schematic,
    1. Move the cursor over the Schematic window.
      The outline for the CDMA_reverse_xmit symbol is attached to the cursor.
    2. Move the cursor near the top left corner of the schematic and click to place the CDMA_reverse_xmit block.
      This block models a CDMA signal source.
    3. Click Esc to remove the symbol from the cursor.

Adding a Resistor to the CDMA Signal Source

Because this example does not use the binary output nodes (i_bin_node and q_bin_node) on the CDMA signal source, connect a resistor between these nodes to avoid unused pin warnings.

  1. In the Libraries column of the Library Browser - Add Instance form, click analogLib to display elements in analogLib.
    If Show Categories is selected, the Everything category is displayed by default and all cells in analogLib are listed in the Cells column.
  2. Scroll through the list of cells in analogLib to locate the resistor cell, res.
  3. Click res in the Cell column.
    The cell res and it’s default view symbol are both selected.
    In the Add Instance form,
    • analogLib displays in the Library field
    • res displays in the Cell field
    • and symbol displays in the View field

    The CDF parameters for the element and their default values appear at the bottom of the form.
  4. Move the cursor over the Schematic window.
  5. Click to place the top resistor terminal in line with the top binary output node (i_bin_out) on the lower right side of the CDMA_reverse_xmit block
  6. Click Esc to remove the symbol from the cursor.

Wiring the Resistor to the CDMA Signal Source

Wire the resistor to the binary outputs, i_bin_node and q_bin_node, of the CDMA signal source.

  1. To wire the resistor to the CDMA_reverse_xmit block, in the Schematic window choose Add - Wire (narrow).
  2. Click i_bin_node on the CDMA_reverse_xmit block then move the cursor and click the top node of the resistor.
  3. Click q_bin_node on the CDMA_reverse_xmit block then move the cursor and click the bottom node of the resistor.
  4. Click Esc to stop wiring.
    The CDMA signal source and resistor wired together appear as follows.

Adding the Driver

Add a driver block to the right of the CDMA signal source block.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the following selections.
    Library Category Cell View

    rfLib

    measurement

    BB_driver

    symbol

    At the top of the Add Instance form,
    • rfLib displays in the Library field,
    • BB_driver displays in the Cell field and
    • symbol displays in the View field.
    • The CDF parameters and their default values appear at the bottom of the Add Instance form.
  4. Move the cursor over the Schematic window.
  5. Click to place the BB_driver to the right of the CDMA_reverse_xmit block. Align the input pins of the driver with the analog output pins of the CDMA signal source.
  6. Click Esc to remove the symbol from the cursor.

Wiring the Signal Source to the Driver

  1. To wire the BB_driver block to the CDMA_reverse_xmit block, in the Schematic window choose Create – Wire (narrow).
  2. Click i_out_node on the CDMA_reverse_xmit block then click I_in on the BB_driver block.
  3. Click q_out_node on the CDMA_reverse_xmit block then click Q_in on the BB_driver block.
  4. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the Driver

Edit the value of the BB_driver CDF parameter dBm-out@1v peak in driver as follows.

  1. Choose Edit – Properties – Objects in the Schematic window.
    The Edit Object Properties form appears. You use this form to change the values of CDF (component description format) properties for the driver and modify the schematic for this simulation.
  2. In the Schematic window, click the BB_driver block.
  3. The Edit Object Properties form changes to display information for the BB_driver block
  4. Change the dBm-out@1v peak in parameter value as follows.
    Parameter Name Value

    dBm-out@1v peak in

    -16


    The driver converts 1 peak volt from the CDMA signal source to −16 dBm referenced to the output resistance of the driver.
  5. Click OK in the Edit Object Properties form.
    The form closes.

Adding the Low Noise Amplifier

Add a low noise amplifier to the right of the driver.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the following selections. (If necessary, click Show Categories at the top of the Library Browser, to display the Category column.)
    Library Category Cell View

    rfLib

    top_dwnBB

    LNA_BB

    symbol

    In the Library Browser, cell LNA_BB and it’s default view symbol are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library field
    • LNA_BB displays in the Cell field
    • symbol displays in the View field

    The CDF parameters for the element and their default values display at the bottom of the LNA_BB Add Instance form.
  4. Move the cursor over the Schematic window. The outline for the LNA symbol is attached to the cursor. Align the input pins of the LNA with the output pins of the driver.
  5. Click to place the LNA_BB block to the right of the BB_driver block.
  6. Click Esc to remove the symbol from the cursor.

Wiring the Driver to the LNA

  1. To wire the LNA_BB block to the BB_driver block, in the Schematic window choose Create - Wire (narrow).
  2. Click I_out on the BB_driver block then click I_in on the LNA_BB block.
  3. Click Q_out on the BB_driver block then click Q_in on the LNA_BB block.
  4. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the LNA

  1. Edit the CDF parameter values for the LNA.
    1. Choose Edit – Properties – Objects in the Schematic window.
      The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for the LNA and modify the schematic for this simulation.
    2. In the Schematic window, click the LNA.
      The Edit Object Properties form changes to display information for the LNA.
    3. Change the CDF parameter values for the LNA as follows.
      Parameter Name Value

      Available pwr gain [dB]

      lna_gain

      Input resistance

      50

      Output resistance

      300

      Input referred IP3 [dBm]

      lna_ip3

      Noise figure [dB]

      10

      am/pm sharpness

      2

      cmp [dBm]

      lna_ip3

      |radians| @ cmp

      .05

      |radians| @ big input

      .7

      {1, 0, -1} for {cw, none, ccw}

      1

  2. Click OK in the Edit Object Properties form.
    The form closes.

Adding a Butterworth Band Pass Filter

Add a Butterworth band pass filter to the right of the low noise amplifier.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    Information for the LNA is still displayed in the form.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the following selection.
    Library Category Cell View

    rfLib

    top_dwnBB

    BB_butterworth_bp

    symbol

    In the Library Browser, cell BB_butterworth_bp and it’s default view are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library field
    • BB_butterworth_bp displays in the Cell field
    • symbol displays in the View field.
    • The CDF parameters for the Butterworth band pass filter and their default values display at the bottom of the Add Instance form.
  4. Move the cursor over the Schematic window. The outline for the filter symbol is attached to the cursor. Align the input pins of the filter with the output pins of the LNA.
  5. Click to place the BB_butterworth_bp block to the right of the LNA_BB block.
  6. Click Esc to remove the symbol from the cursor.

Wiring the LNA to the Filter

  1. To wire the BB_butterworth_bp block to the LNA_BB block, in the Schematic window choose Create – Wire (narrow).
  2. Click I_out on the LNA_BB block then click ini on the BB_butterworth_bp block.
  3. Click Q_out on the LNA_BB block then click inq on the BB_butterworth_bp block.
  4. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the Band Pass Filter

Edit the CDF parameter values for the Butterworth band pass filter.

  1. Choose Edit – Properties – Objects in the Schematic window.
    The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for the filter and modify the schematic for this simulation.
  2. In the Schematic window, click the filter.
    The Edit Object Properties form changes to display information for the filter.
  3. Edit the parameter values to match those in Table 11-2.
  4. Click OK.

    Table 11-2 CDF Parameter Values for the Butterworth Filter
    Parameter Name Value

    Filter order

    3

    Input impedance

    50

    Output impedance

    50

    Center frequency (Hz)

    frf

    Relative bandwidth

    rf_rbw

    Insertion loss (dB)

    3

    Carrier frequency

    frf

Specify the Carrier frequency parameter value for the baseband equivalent model of the Butterworth band pass filter, just as you do for any reactive element. As shown in Figure 11-6, the carrier frequency is used to compute speed voltages. Because filters are built up from inductors and capacitors which have speed voltages, you must specify the carrier frequency for filters.

When a filter follows an RF-to-IF mixer, its Carrier frequency parameter value is the IF frequency.

Adding an RF-to-IF Mixer

Add an RF-to-IF mixer (dwn_cnvrt) block to the right of the bandpass filter block.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the selections indicated in Table 11-3.

    Table 11-3 Library Browser selections for the RF to IF Mixer
    Library Category Cell View

    rfLib

    top_dwnBB

    dwn_cnvrt

    symbol

    In the Library Browser, cell dwn_cnvrt (the RF-to-IF mixer) and it’s default view symbol are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library field
    • dwn_cnvrt displays in the Cell field
    • symbol displays in the View field.

    The CDF parameters for the down converter and their default values display at the bottom of the form.
  4. Move the cursor over the Schematic window. The outline for the RF-to-IF Mixer symbol is attached to the cursor. Align the input pins of the mixer with the output pins of the filter.
  5. Click to place the dwn_cnvrt block to the right of the BB_butterworth_bp block.
  6. Click Esc to remove the symbol from the cursor.

Grounding the phase_err Pin on the Mixer

It is necessary to ground the phase error (phase_err) pin on the bottom of the RF-to-IF mixer.

  1. In the Schematic window, choose Add – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, type
    • analogLib in the Library field
    • gnd in the Cell field
    • symbol in the View field.
  3. Move the cursor over the Schematic window.
  4. Click to place the ground terminal in line with the phase error node (phase_err) on the bottom of the dwn_cnvt block.
  5. Click Esc to remove the symbol from the cursor.

Wiring the Filter and Ground to the Mixer

  1. To wire the dwn_cnvrt block to the BB_butterworth_bp block and the ground, in the Schematic window choose Create - Wire (narrow).
  2. Click outi on the BB_butterworth_bp block then click I_in on the dwn_cnvrt block.
  3. Click outq on the BB_butterworth_bp block then click Q_in on the dwn_cnvrt block.
  4. Click the port on the gnd block then click phase_err on the dwn_cnvrt block.
  5. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the RF-to-IF Mixer

  1. Edit the CDF parameter values for the RF-to-IF mixer (dwn_cnvrt) as listed in Table 11-4.
    1. Choose Edit – Properties – Objects in the Schematic window.
      The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for dwn_cnvrt and modify the schematic for this simulation.
    2. In the Schematic window, click dwn_cnvrt.
      The Edit Object Properties form changes to display information for dwn_cnvrt.
    3. Change the parameter values to match those in Table 11-4.
    4. Click OK.

      Table 11-4 CDF Parameter Values for the RF-to-IF Mixer
      Parameter Name Value

      available power gain[dB]

      if_mx_gain

      Input resistance

      50

      output resistance

      50

      input referred ip3[dBm]

      if_mx_ip

      noise figure [dB]

      10

      RF frequency

      frf

      LO frequency

      flo1

      AM/PM input point[dBm]

      -30

      phase shift at cmp[rad]

      .7

      phase shift at infinity

      2

      sharpness factor

      2

      {1,0,−1} = {cw,none,ccw}

      0

Adding Another Butterworth Bandpass Filter

Add another Butterworth band pass filter block to the right of the RF-to-IF Mixer block.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the following selection.
    Library Category Cell View

    rfLib

    top_dwnBB

    BB_butterworth_bp

    symbol

    In the Library Browser, cell BB_butterworth_bp and it’s default view are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library field
    • BB_butterworth_bp displays in the Cell field
    • symbol displays in the View field.

    The CDF parameters for the Butterworth band pass filter and their default values display at the bottom of the Add Instance form.
  4. Move the cursor over the Schematic window. The outline for the filter symbol is attached to the cursor. Align the input pins of the filter with the output pins of the LNA.
  5. Click to place the BB_butterworth_bp block to the right of the LNA_BB block.
  6. Click Esc to remove the symbol from the cursor.

Wiring the Mixer to the Filter

  1. To wire the BB_butterworth_bp block to the dwn_cnvrt block, in the Schematic window choose Create - Wire (narrow).
  2. Click I_out on the dwn_cnvrt block then click ini on the BB_butterworth_bp block.
  3. Click Q_out on the dwn_cnvrt block then click inq on the BB_butterworth_bp block.
  4. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the Band Pass Filter

  1. Edit the CDF parameter values for the Butterworth band pass filter as listed in Table 11-5.
    1. Choose Edit – Properties – Objects in the Schematic window.
      The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for the filter and modify the schematic for this simulation.
    2. In the Schematic window, click the filter.
      The Edit Object Properties form changes to display information for the filter.
    3. Change the parameter values to match those in Table 11-5.
    4. Click OK.

      Table 11-5 CDF Parameter Values for the Second Butterworth Filter
      Parameter Name Value

      Filter Order

      3

      Input impedance

      50

      Output impedance

      50

      Center frequency (Hz)

      −frf+flo1

      Relative bandwidth

      if_rbw

      Insertion loss (dB)

      1

      Carrier frequency

      −frf+flo1

As for the first band pass filter, specify the carrier frequency for the baseband equivalent model of the Butterworth band pass filter, just as you do for any reactive element. As shown in Figure 11-6, the carrier frequency is used to compute speed voltages. Because filters are built up from inductors and capacitors which have speed voltages, you must specify the carrier frequency for filters.

When a filter follows an RF-to-IF mixer, its carrier frequency is the IF frequency. The carrier frequency is the frequency to which the baseband signals are referenced. The center frequency of the bandpass filter does not have to equal the carrier frequency. The center frequency is the frequency for which a filter is designed.

Adding an IQ Demodulator

Add an IQ Demodulator (IQ_demod_BB) block to the right of the bandpass filter block.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form,
    1. If necessary, click Show Categories to display the Category column.
    2. Click rfLib to display elements in rfLib. The Everything category is displayed by default and all cells in rfLib are listed in the Cells column.
    3. In the Category column, click top_dwnBB to display cells in the top_dwnBB category.
    4. In the Cell column, click IQ_demod_BB.

    In the Library Browser, cell IQ_demod_BB (the IQ demodulator) and it’s default view symbol are both selected.
    At the top of the Add Instance form, rfLib displays in the Library field, IQ_demod_BB displays in the Cell field and symbol displays in the View field. The CDF parameters for the IQ demodulator and their default values display at the bottom of the form.
  4. Move the cursor over the Schematic window. The outline for the IQ demodulator symbol is attached to the cursor. Align the input pins of the IQ demodulator with the output pins of the filter and click to place the IQ_demod_BB block to the right of the second BB_butterworth_bp block.
  5. Click Esc to remove the symbol from the cursor.

Grounding the phase_err Pin on the IQ Demodulator

It is necessary to ground the phase error (phase_err) pin on the bottom of the IQ demodulator.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, type
    • analogLib in the Library field
    • gnd in the Cell field
    • symbol in the View field.
  3. Move the cursor over the Schematic window.
  4. Click to place the ground terminal in line with the phase error node (phase_err) on the bottom of the IQ_demod_BB block.
  5. Click Esc to remove the symbol from the cursor.

Wiring the Filter and Ground to the IQ Demodulator

  1. To wire the IQ_demod_BB block to the BB_butterworth_bp block and the ground, in the Schematic window choose Add - Wire (narrow).
  2. Click outi on the BB_butterworth_bp block then click I_in on the IQ_demod_BB block.
  3. Click outq on the BB_butterworth_bp block then click Q_in on the IQ_demod_BB block.
  4. Click the port on the gnd block then click phase_err on the IQ_demod_BB block.
  5. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the IQ Demodulator

  1. Edit the CDF parameter values for the IQ Demodulator (IQ_demod_BB) as listed in Table 11-6.
    1. Choose Edit – Properties – Objects in the Schematic window.
      The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for IQ_demod_BB and modify the schematic for this simulation.
    2. In the Schematic window, click IQ_demod_BB.
      The Edit Object Properties form changes to display information for IQ_demod_BB.
    3. Change the parameter values to match those in Table 11-6.
    4. Click OK.

      Table 11-6 CDF Parameter Values for the IQ Demodulator
      Parameter Name Value

      available I-mixer gain[dB]

      0

      available Q-mixer gain[dB]

      0

      Input resistance

      50

      output resistance

      50

      I−[dBm] input referred IP3

      40

      Q−[dBm] input referred IP3

      40

      noise figure [dB]

      2

      quadrature error

      0

      I−sharpness factor

      2

      Q−sharpness factor

      2

      I_cmp

      −30

      Q_cmp

      −30

      I−radians@I_cmp

      .7

      Q−radians@Q_cmp

      .7

      I−radians@big I-input

      2

      Q−radians@big Q-input

      2

      I {1,0,−1} for {cw,none,ccw}

      0

      Q {1,0,−1} for {cw,none,ccw}

      0

Adding Two Butterworth Lowpass Filters

  1. Add two Butterworth low pass filters to the right of the IQ demodulator block.
    • Align one filter with the demodulator’s i_out pin.
    • Align the other filter with its q_out pin.
  2. In the Schematic window, choose Create – Instance to display the Add Instance form.
  3. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  4. In the Library Browser - Add Instance form, make the following selections.
    Library Category Cell View

    rfLib

    top_dwnPB

    butterworth_lp

    symbol

    In the Library Browser, cell butterworth_lp and it’s default view are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library field
    • butterworth_lp displays in the Cell field
    • symbol displays in the View field.
    • The CDF parameters for the Butterworth low pass filter and their default values display at the bottom of the Add Instance form.
  5. Move the cursor over the Schematic window. The outline for the butterworth low pass filter symbol is attached to the cursor.
    Align the in pin of the first butterworth low pass filter with the I_out pin (the top pin) of the IQ demodulator and click to place the filter close to the demodulator. Align the in pin of the second butterworth low pass filter with the Q_out pin (the bottom pin) of the IQ demodulator. You have to place it further from the demodulator to align it with the Q_out pin.
  6. Click Esc to remove the symbol from the cursor.

Wiring the IQ Demodulator to the Filters

  1. To wire the IQ_demod_BB block to the butterworth_lp blocks, in the Schematic window choose Add - Wire (narrow).
  2. Click I_out on the IQ_demod_BB block then click in on the first butterworth_lp block.
  3. Click Q_out on the IQ_demod_BB block then click in on the second butterworth_lp block.
  4. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for Both Low Pass Filters

  1. Edit the CDF parameter values for the Butterworth low pass filters as listed in Table 11-7.
    1. Choose Edit – Properties – Objects in the Schematic window.
      The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for each filter and modify the schematic for this simulation.
    2. In the Schematic window, click the first low pass filter.
      The Edit Object Properties form changes to display information for the filter.
    3. Change the parameter values to match those in Table 11-7.

      Table 11-7 CDF Parameter Values for the Butterworth Low Pass Filters
      Parameter Name Value

      Filter Order

      3

      Input impedance

      50

      Output impedance

      50

      Corner frequency (Hz)

      10M

      Insertion loss (dB)

      0
    4. Click Apply.
    5. In the Schematic window, click the second low pass filter.
      The Edit Object Properties form displays the information you entered for the filter as shown in Table 11-7.
    6. Click OK.

Adding an Instrumentation Block

Add an instrumentation block (offset_comms_instr) block to the right of the low pass filter blocks.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the following selections. (If necessary, click Show Categories at the top of the Library Browser, to display the Category column.)
    Library Category Cell View

    rfLib

    measurement

    offset_comms_instr

    symbol

    In the Library Browser, cell offset_comms_instr and it’s default view symbol are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library
    • offset_comms_instr displays in the Cell field
    • symbol displays in the View field

    The CDF parameters for the offset_comms_instr and their default values display at the bottom of the form.
  4. Move the cursor over the Schematic window. The outline for the offset_comms_instr block symbol is attached to the cursor. Align the I_in and Q_in pins of the offset_comms_instr block with the out pins of the butterworth low pass filters and click to place the offset_comms_instr block to the right of the low pass filter blocks.
  5. Click Esc to remove the symbol from the cursor.

Grounding the Reference Pins on the Instrumentation Block

It is necessary to ground the reference pins (I_ref and Q_ref) pin near the lower left corner of the instrumentation block.

Grounding the phase_err Pin on the Mixer

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, type
    • analogLib in the Library field
    • gnd in the Cell field
    • symbol in the View field.
  3. Move the cursor over the Schematic window.
  4. Click to place the ground terminal in line with the Q_ref node on the bottom of the offset_comms_instr block.
  5. Click Esc to remove the symbol from the cursor.

Wiring the Filter and Ground to the Instrumentation Block

  1. To wire the low pass filters to the offset_comms_instr block and the ground, in the Schematic window choose Add - Wire (narrow).
  2. Click out on the upper butterworth_lp block (the low pass filter connected to the I_out node on the IQ demodulator) then click I_in on the offset_comms_instr block.
  3. Click out on the lower butterworth_lp block (the low pass filter connected to the Q_out node on the IQ demodulator) then click Q_in on the offset_comms_instr block.
  4. Click the port on the gnd block then click the Q_ref node on the offset_comms_instr block.
  5. Click the port on the gnd block then click the I_ref node on the offset_comms_instr block.
  6. Click Esc to stop wiring.
    The schematic now appears as follows.

Modifying Parameter Values for the Instrumentation Block

  1. Edit the CDF parameter values for the offset_comms_instr as listed in Table 11-8.
    1. Choose Edit – Properties – Objects in the Schematic window.
      The Edit Object Properties form appears. You use this form to change the list of CDF (component description format) properties for offset_comms_instr and modify the schematic for this simulation.
    2. In the Schematic window, click the offset_comms_instr block.
      The Edit Object Properties form changes to display information for offset_comms_instr block.
    3. Change the parameter values to match those in Table 11-8.
    4. Click OK.

      Table 11-8 CDF Parameter Values for the Instrumentation Block
      Parameter Name Value

      symbols per second

      1228800

      I-sampling delay (secs)

      134n

      number of symbols

      2

      max eye-diag volts

      1

      min eye volts

      −1

      number of hstgm bins

      100

      I-noise (volts2)

      0

      Q-noise (volts2)

      0

      statistics start time

      30u

      input resistance

      50

Adding an Instrumentation Terminator

Add an instrumentation termination (instr_term) block to the right of the instrumentation block. The instr_term block terminates the outputs on the instrumentation block and prevents unused pin warnings.

  1. In the Schematic window, choose Create – Instance to display the Add Instance form.
    The Add Instance form appears. It may be empty or it may display information for a previously added element.
  2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
  3. In the Library Browser - Add Instance form, make the following selections. (If necessary, click Show Categories at the top of the Library Browser, to display the Category column.)
    Library Category Cell View

    rfLib

    measurement

    instr_term

    symbol

    In the Library Browser, cell instr_term and it’s default view symbol are both selected.
    At the top of the Add Instance form,
    • rfLib displays in the Library
    • instr_term displays in the Cell field
    • symbol displays in the View field

    There are no CDF parameters for the instr_term cell.
  4. Move the cursor over the Schematic window. The outline for the instr_term symbol is attached to the cursor. Move the instr_term block to the right of the instrumentation block and align the input pins of the instrumentation termination block with the output pins of the instrumentation block.
  5. Click to place the instr_term block.
  6. Click Esc to remove the symbol from the cursor.

Wiring the Termination Block to the Instrumentation Block

  1. To wire the instrumentation (offset_comms_instr) block to the Instrumentation terminator (instr_term) block, in the Schematic window choose Create - Wire (narrow).
  2. Wire the aligned pins straight across.
  3. Click Esc to stop wiring.
    The schematic should look as follows.
  4. In the Schematic window, choose File – Check and Save.
    The completed schematic is verified and saved.

The schematic for the complete receiver model should look like the one in Figure 11-7.

Figure 11-7 Completed receiver model

Setting Variable Values for the Receiver Schematic

Copy the variables you entered as CDF parameters for the individual blocks from the receiver schematic to the ADE window. Then edit each variable to give it the value specified in Table 11-9.

  1. In ADE Explorer, choose Variables – Copy From Cellview to copy the variables from the receiver schematic to the Design Variables in the Setup Assistant in ADE Explorer.
    The copied variables display in Design Variables in the ADE window.
  2. In the ADE window, choose Variables – Edit to open the Editing Design Variables form.

Adding the Values to the Copied Variables

In the Editing Design Variables form, one by one, select each variable in the Table of Design Variables and associate with each one, the value listed in Table 11-9.

Table 11-9 Values for Receiver Variables
Variable Value

lna_gain

15

lna_ip3

−5

if_mx_gain

10

if_mx_ip

35

frf

2.14G

flo1

2.354G

if_rbw

200m

rf_rbw

100m

To associate a value with a design variable

  1. In the Design Variables table, click lna_gain.
    lna_gain displays in the Name field.
  2. In the Value (Expr) field, enter the number 15, the value from Table 11-9.
  3. Click Change to list the variable name and its value from the Table of Design Variables.
  4. Repeat these steps for the remaining variables listed in the Design Variables table to associate the values from Table 11-9 with the variable names.
  5. Click OK in the Editing Design Variables form after you have added all the variable values.
    The table of Design Variables in the ADE window is updated and the Editing Design Variables form is closed.

Setting Up and Running a Transient Analysis

  1. In the ADE window, choose Analyses – Choose to display the Choosing Analyses form.
  2. In the Choosing Analyses form, if necessary, click tran to select a transient analysis.
  3. In the Choosing Analyses form, enter 130u in the Stop Time field.
  4. Highlight moderate for Accuracy Defaults (errpreset).
  5. In the Choosing Analyses form, click Options to display the Transient Options form.
  6. In the Transient Options form, enter 30u in the outputstart field.
    By delaying the output start, you remove start-up transients from the eye-diagrams and scatter plots.
  7. Click OK in the Transient Options form.
  8. Click OK in the Choosing Analyses form.
  9. If you have not already done so, set up the simulator and model libraries with the following steps.
    1. Set the simulator options from the Simulator window as described in “Choosing Simulator Options”.
    2. Set up the model libraries from the Simulator window as described in “Setting Up Model Libraries”.
  10. In the ADE window, choose Simulation – Netlist and Run.
    Messages display in the CIW. The simulation log window opens. Watch for messages stating that the simulation has completed successfully.
    Watch the CIW for messages stating the simulation is running and that it has completed successfully.

Examining the Results: Eye Diagram, Histogram, and Scatter Plot

In this section we examine the results of the transient analysis of the receiver.

Plotting the Eye Diagram (and Transient Response)

First plot an eye diagram.

  1. In the ADE window, choose Results – Direct Plot – Transient Signal.
    The Virtuoso Schematic Editing window appears.
  2. Following the prompts at the bottom of the window,
    > Select nodes or terminals, press <esc> to finish selection
    1. In the Schematic window, click the sawtooth net from the instrumentation (offset_comms_instr) block.
    2. Click the I_eye net from the instrumentation (offset_comms_instr) block.
    3. Press Esc to indicate that you have finished selecting outputs.
      This opens a waveform window and creates a plot of the Transient Response of the net.
  3. In the waveform window, double-click the X axis.
    The Axis Attributes form displays:
    1. In the Plot vs field, select the sawtooth net, such as /net15.
    2. Click OK.

    You see the eye-diagram shown in Figure 11-8.
    Figure 11-8 Eye-diagram
    The I-sampling delay parameter in the instrumentation block (I_del) is chosen with respect to this eye diagram. The delay is the time when the eye opens the widest.
    The instrumentation block samples the input waveforms with this delay to compute all statistics and to produce scatter plots.
  4. In the waveform window, choose File – Close.
    The waveform window closes.

Generate the Histogram

Now generate a histogram of the I-voltage at the sampling times.

  1. In the ADE window, choose Results – Direct Plot – Transient Signal.
    The Virtuoso Schematic Editing window appears.
  2. Following the prompts at the bottom of the window,
    1. Click the eye_hist net from the instrumentation (offset_comms_instr) block.
    2. Click the eye_count_hist net from offset_comms_instr.
    3. Press Esc to indicate that you have finished selecting outputs.
      This creates a plot in the waveform window.
  3. In the waveform window, double-click the X axis.
    The Axis Attributes form displays:
    1. In the Plot vs field, select the eye_hist output, such as /net17.
    2. Click OK.

    This creates an unintelligible intermediate plot in the waveform window.
  4. In the waveform window, double-click the trace in the graph.
    The Trace Attributes form displays.
    1. In the Type/Style cyclic field, select Bars.
    2. Click OK.

    You see a plot like Figure 11-9.
    Figure 11-9 Histogram
  5. In the waveform window, choose File – Close.
    The waveform window closes.

Generating the Scatter Plot

Generate a scatter plot of the received symbols.

  1. In the ADE window, choose Results – Direct Plot – Transient Signal.
    This displays the waveform window.
  2. Following the prompts at the bottom of the waveform window,
    In the Schematic window:
    1. Click the I_scatter output from the instrumentation (offset_comms_instr) block.
    2. Click the Q_scatter output from offset_comms_instr.
    3. Click Esc to indicate that you have finished selecting outputs.
      This creates a plot in the waveform window.
  3. In the waveform window, double-click the X axis.
    The Axis Attributes form displays:
    1. In the Plot vs field, select the I_scatter output, such as /net22.
    2. Click OK.
  4. In the waveform window, double-click the trace in the graph.
    The Trace Attributes form displays.
    1. In the Type/Style cyclic field, select Points.
    2. Click OK.

    You see a scatter plot like Figure 11-10.
    Figure 11-10 Scatter Plot
  5. In the waveform window, choose File – Close.
    The waveform window closes.

The Various Instrumentation Blocks

The CDMA source (CDMA_reverse_xmit) produced offset QPSK symbols. Offset QPSK modulation avoids traversing the origin by staggering the digital changes in the I and Q signals. Running the baseband trajectory through the origin increases spectral regrowth in the transmitters.

The instrumentation block (offset_comms_instr) samples the I and Q signals at different times then plots the two staggered samples against each other. The resulting scatter plot shows the received symbols. A scatter plot of the unstaggered samples reveals only what is happening in one dimension, either the I or Q dimension.

For non-offset QPSK and QAM modulation schemes, use the comms_instr instrumentation block instead of the offset_comms_instr block.

Measuring RMS EVM

You can use the same instrumentation block (offset_comms_instr) to compute root-mean-squared error vector magnitude (RMS EVM). The error vector is the vectorial difference between the ideal received symbol and the actual received symbol.

RMS EVM is one measure of a receiver’s quality. RMS EVM can account for as much or as little distortion and noise as you like. The trick is to figure out where the ideal received symbol lies. You can do this using the I_ref and Q_ref inputs to the offset_comms_instr instrumentation block.

To calculate RMS EVM, you

Constructing the Ideal Receiver Chain

The ideal receiver chain (the duplicated and modified receiver chain) is driven from the same input, the CDMA_reverse_xmit block, as the original receiver chain. The output of the ideal receiver chain drives the instrumentation block’s I_ref and Q_ref inputs.

In the ideal receiver chain, you copy the first receiver chain and make every block ideal.

  1. Remove the gnd from the I_ref and Q_ref pins on the instrumentation block.
    1. In the Schematic window, choose Edit - Delete.
    2. In the Schematic window, click each wire and the Gnd symbol attached to the I_ref and Q_ref pins.
    3. Click esc to stop deleting.
  2. Duplicate the receiver chain from the BB_driver to the IQ_demod_BB inclusive. Do not duplicate the filters. Follow the prompts at the bottom of the Schematic window.
    1. In the Schematic window, choose Edit – Copy.
    2. In the Schematic window, draw a box around the blocks to copy by clicking to the left of and above the BB_driver block and dragging the cursor to a point below and to the right of the IQ_demod_BB block. Click again to complete the box.
      The blocks within the box are highlighted.
    3. Click within the highlighted area.
      A copy of the highlighted blocks in the receiver chain now moves with the cursor.
    4. Place the duplicate receiver chain so that the output pins on the IQ_demod_BB are in line with the I_ref and Q_ref pins on the instrumentation block.
  3. Wire the duplicate receiver chain to the CDMA signal source (CDMA_reverse_xmit) and the instrumentation block (offset_comms_instr).
    1. In the Schematic window, choose Create- Wire (narrow).
    2. Connect the IQ_demod_BB outputs on the duplicate receiver to the I_ref and Q_ref pins on the instrumentation block.
    3. Connect the output pins on CDMA_reverse_xmit to the input pins of the duplicate BB_driver. This drives the duplicate receiver from the CDMA signal source.
    4. Click esc to stop wiring.

The schematic with the duplicate receiver chain wired up looks like Figure 11-11.

Figure 11-11 Receiver Model with Duplicated Receiver Chain

Modifying Parameter Values to Make the Blocks Ideal

Now modify the parameter values for each block in the duplicate receiver chain to create ideal blocks. Block names, parameter names, and parameter values are given in Table 11-10.

Table 11-10 Parameter Values to Create an Ideal Receiver
Block Names Parameter Names New Parameter Values

LNA_BB

Input referred IP3 [dBm] {1,0,-1} for {cw, none, ccw}

100
0

BB_butterworth_bp

Cell Name

BB_loss

dwn_cnvrt

Input referred IP3 [dBm]

100

BB_butterworth_bp

Cell Name

BB_loss

IQ_demod_BB

I-[dBm] Input referred IP3
Q-[dBm] Input referred IP3

100
100
  1. In the Schematic window, choose Edit – Properties – Objects to open the Edit Object Properties form.
  2. In the Schematic window, select the LNA_BB block.
    The Edit Object Properties form changes to display properties for the LNA_BB block.
    1. Set Input referred IP3 [dBm] to 100.
    2. Set {1, 0,-1} for {cw, none, ccw} to 0. (This eliminates AM/PM conversion.)
    3. Click Apply.
  3. In the Schematic window, select the first RF BB_butterworth_bp block.
    The Edit Object Properties form changes to display properties for the BB_butterworth_bp block.
    1. Change the Cell Name to BB_loss.
    2. Click Apply.

    The properties and symbol change to those for the BB_loss block. The sole purpose of the BB_loss model is to replace a filter in an RMS EVM analysis.
    The Reference impedance for the BB_loss block should equal the Output impedance of the BB_butterworth_bp bandpass filter block it replaces. The value should be 50 ohms for both blocks and you should not have to change it.
    The BB_loss model retains the filter’s loss but eliminates the filter’s dynamics so you can see what, if any, affect the filter has on EVM through inter-symbol interference. To eliminate the loss as well as the dynamics, you might even replace the filter with straight wires. This example uses the BB_loss block instead.
  4. In the Schematic window, select the dwn_cnvrt block.
    The Edit Object Properties form changes to display properties for the dwn_cnvrt block
    1. Set Input referred IP3 [dBm] to 100.
    2. Click Apply.
  5. In the Schematic window, select the second BB_butterworth_bp block.
    The Edit Object Properties form changes to display properties for the BB_butterworth_bp block
    1. Change the Cell Name to BB_loss.
    2. Click Apply.
  6. In the Schematic window, select the IQ_demod_BB block.
    The Edit Object Properties form changes to display properties for the IQ_demod_BB block
    1. Set I-[dBm] input referred IP3 to 100.
    2. Set Q-[dBm] input referred IP3 to 100.
    3. Click Apply.
  7. In the Edit Object Properties form, click OK to close the form.
  8. In the Schematic window, choose File – Check and Save to check and save your modifications to the circuit.

Set Up and Run a Transient Analysis

Set up and run a transient analysis as described in “Setting Up and Running a Transient Analysis”. Set the Stop Time to 130u and the outputstart option to 30u. Click OK in both the Transient Options and Choosing Analyses forms. Choose Simulation – Netlist and Run to run the transient analysis.

Look for messages in the CIW stating that the simulation is starting. Watch the simulation log window for messages that the simulation has completed successfully.

Plot the RMS EVM Output

After the simulation, plot the RMS_EVM output of the instrumentation block.

  1. In the ADE window, choose Results – Direct Plot – Transient Signal.
    This displays the waveform window.
  2. Following the prompts at the bottom of the waveform window,
    1. In the schematic, click the rms_EVM output net from the instrumentation (offset_comms_instr) block.
    2. Click Esc to indicate that you have finished selecting outputs.
      This creates the RMS EVM plot in the waveform window as shown in Figure 11-12.
      Figure 11-12 RMS EVM
    The RMS EVM trace starts at 30us, which is the statistics start time parameter of the instrumentation block. The statistics start time parameter keeps start-up transients out of the statistics.
    The trace settles out at 25.84 Volts. This means that after 130us of data is collected, and ignoring the first 30us, the RMS EVM is 25.84%. The EVM measurement is normalized to the RMS magnitude of the ideal symbol then multiplied by 100 to express the measurement as a percentage.
  3. In the waveform window, choose File – Close.

Computing Minimized RMS Noise Using the Optimizer

There is one more construction step before proceeding to the Circuit Optimizer application. You set up the Circuit Optimizer to minimize RMS noise subject to performance constraints. This step replicates the receiver chain yet one more time to generate the noise measurement.

  1. Duplicate the original receiver chain from the BB_driver up to and including both low pass filters (butterworth_lp). Follow the prompts at the bottom of the Schematic window.
    1. In the Schematic window, choose Edit – Copy.
    2. In the Schematic window, draw a box around the blocks to copy by clicking to the left of and above the BB_driver block and dragging the cursor to a point below and to the right of the butterworth_lp filter blocks. Click again to complete the box.
      The blocks within the box are highlighted.
    3. Click within the highlighted area.
      A copy of the highlighted blocks in the receiver chain now moves with the cursor.
    4. Place the duplicate receiver chain above the original receiver chain.
  2. In the duplicate receiver chain, ground the Q_in pin on the BB_driver block.
    1. In the Schematic window, choose Create – Wire.
    2. Click the Q_in pin and run the wire to the Gnd symbol below the dwn_cnvrt block.
    3. Click the Gnd symbol below the dwn_cnvrt block.
    4. Click esc to stop wiring.
  3. Add a 50mV DC voltage source to the left of the BB_driver block to drive the I_in pin on the BB_driver block. At the same time add a gnd symbol below the port in the schematic.
    1. In the Schematic window, choose Add – Instance to display the Add Instance form.
    2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
    3. In the Library Browser - Add Instance form, click analogLib.
    4. Scroll the elements in the Cell column and click port.
    5. The outline for the port symbol is attached to the cursor. Move the port symbol to the left of the BB_driver block and click to place the port symbol.
    6. Return to the Library Browser - Add Instance form and scroll the elements in the Cell column and click gnd.
    7. The outline for the gnd symbol is attached to the cursor. Move the gnd symbol below the port symbol and click to place it there.
    8. Click Esc to remove the gnd symbol from the cursor.
  4. In the Schematic window, choose Edit – Object – Properties to modify the port symbol using the Edit Object Properties form.
    1. In the Schematic window, click the port symbol.
      The Edit Object Properties form changes to display information for the port symbol.
    2. In the Source Type cyclic field, select dc.
    3. In the DC Voltage field, enter 50m.
    4. Highlight Display small signal params to display small signal parameters.
    5. In the AC Magnitude field type 1V.
    6. In the AC Phase field type 0.
    7. Click OK in the Edit Object Properties form.
  5. Load the low pass filters with a res_BB model from the top_dwnBB category of rfLib. Use the default parameters and ground the output pins.
    1. In the Schematic window, choose Add – Instance to display the Add Instance form.
    2. In the Add Instance form, click Browse to display the Library Browser - Add Instance form.
    3. In the Library Browser - Add Instance form, click rfLib.
    4. Scroll the elements in the Cell column and click res_BB.
      The outline for the res_BB symbol is attached to the cursor.
    5. Move the res_BB symbol to the right of the two low pass filters (butterworth_lp) and click to place the res_BB symbol.
    6. Return to the Library Browser - Add Instance form and click analogLib.
    7. Scroll the elements in the Cell column and click gnd.
      The outline for the gnd symbol is attached to the cursor.
    8. Move the gnd symbol to the right of the res_BB symbol and click to place it there.
    9. Click Esc to remove the symbol from the cursor.
  6. In the duplicate receiver chain, wire the port, the res_BB block, and their gnd blocks.
    1. In the Schematic window, choose Add – Wire.
    2. Click the I_in pin on the BB_driver, then click the top pin on the port.
    3. Click the bottom pin on the port, then click the gnd pin just below it.
    4. Click the out pin on the top butterworth_lp filter, then click the I_in pin on the res_BB block.
    5. Click the out pin on the lower butterworth_lp filter, then click the Q_in pin on the res_BB block.
    6. Click the I_out pin on the res_BB block. Then click the top pin on the gnd located to it’s right.
    7. Click the Q_out pin on the res_BB block. Then click the top pin on the same gnd.
    8. Click esc to stop wiring.
  7. In the Schematic window, choose File – Check and Save to check and save the schematic.

The schematic with the third receiver chain is shown in Figure 11-13.

Figure 11-13 Schematic with Noise Generating Receiver

Set Up and Run Transient and Noise Analyses

Set up a transient analysis as described in “Setting Up and Running a Transient Analysis”. Set the Stop Time to 130u and the outputstart option to 30u and make sure that the transient analysis is enabled.

Set up a noise analysis as follows:

  1. In the Choosing Analyses form, click noise to select a noise analysis.
  2. For Sweep Variable, click Frequency.
  3. For Sweep Range, click Start-Stop.
  4. Set up the analysis to sweep frequency from 0 to100 MHz.
    1. For the starting frequency, in the Start field enter 0.
    2. For the stop frequency, in the Stop field enter 100M.
  5. Set up the Output Noise source.
    1. In the Output Noise cyclic field, select voltage.
    2. To select the Positive Output Node, click Select next to the Positive Output Node field. Then, in the Schematic window, click the net next to the I_in pin on the res_BB block.
    3. To select the Negative Output Node, click Select next to the Negative Output Node field. Then, in the Schematic window, click the net next to the I_out pin on the res_BB block.
  6. Set up the Input Noise source.
    1. In the Input Noise cyclic field, select port.
    2. To select the Input Port Source, click Select next to the Input Port Source field. Then, in the Schematic window, click the DC input port model.
  7. Click Enabled.
    The Output Noise and Input Noise sections of the Noise analysis form look as follows. (The net instance numbers might be different, however.)
  8. Verify that Enabled is highlighted and click OK in the Choosing Analyses form.
  9. In the ADE window, check the Analysis area to verify that both the transient and noise analyses are set up properly and that they are both enabled.
  10. In the ADE window, choose Simulation – Netlist and Run to start the simulations.
    Watch the messages in the CIW to verify that everything is set up properly and that the simulations start. Check the simulation log window to see that the simulations run and complete properly.

Set Up to Run the Circuit Optimizer

  1. In the ADE window, choose Tools – Calculator to open the calculator window.
  2. In the ADE window, choose Tools – Optimization to open the Circuit Optimizer window.

Add the First Goal

  1. In the calculator window’s function panel, select rmsNoise.
  2. When the RMS Noise panel opens,
    1. In the From field, enter 0.
    2. In the To field, enter 100M.
    3. Click OK.
      The expression
      rmsNoise(0,100M)
      displays in the buffer of the calculator window.
  3. In the Circuit Optimizer window, choose Goals – Add to add the first goal.
    The Adding Goals form opens.
  4. Fill in the Adding Goals form.
    1. In the Name field, type rmsNoise.
    2. Click the Get Expression button to the right of the Calculator label.
      The expression rmsNoise(0 100000000) displays in the Expression field.
    3. Ensure that the Direction is minimize.
      The default for the Optimizer is to minimize goals.
    4. In the Target field, enter 0.1u.
    5. In the Acceptable field, enter 20u.
    6. Verify that the form is enabled.
      The Adding Goals form looks like this.
    7. Click OK.

    The first goal is added to the Circuit Optimizer window.

Add the Second Goal

  1. In the calculator window, under the tran tab, click the vt button.
    The Schematic Editing window becomes active.
  2. In the Schematic window, click the rms_EVM output net of the instrumentation block.
    An expression similar to VT("/net24") displays in the calculator buffer.
  3. In the calculator window’s function panel, select value.
    When the Value panel appears
    1. Enter 130u in the Interpolate At field.
    2. Click OK.
      The expanded expression value(VT("/net24") 130u ) displays in the buffer of the calculator window.
  4. In the Circuit Optimizer, choose Goals – Add.
    When the Adding Goals form opens
    1. In the Name field, enter evm.
    2. Click the Get Expression button to the right of the Calculator label.
      An expression similar to
      value(VT("/net24") 0.00013)
      displays in the Expression field.
    3. In the Direction cyclic field, select <=
    4. In the Target field, enter 25.
    5. In the Acceptable field, enter 10.
    6. Click the % within Target button.
    7. Verify that Enabled is active.
      The Adding Goals form looks like this.
    8. Click OK.
      The second goal is added to the Circuit Optimizer window.

Add the Third Goal

  1. In the calculator window, click Clear.
    The buffer is cleared.
  2. Under the tran tab, click the vt button.
    The Schematic Editing window becomes active.
  3. In the Schematic window, click the I_in pin of the instrumentation block.
    An expression similar to VT("/net14") displays in the buffer of the calculator window.
  4. In the calculator window’s function panel, select rms.
    An expanded expression similar to
    rms(VT("/net14"))
    displays in the buffer of the calculator window.
    The objective is to keep the rms value of this signal level above 300 mV. Note that all goals must be scalars.
  5. In the Circuit Optimizer, choose Goals - Add.
    The Adding Goals form opens.
  6. Fill in the fields of the Adding Goals form.
    1. In the Name field, enter sig_level.
    2. Click the Get Expression button to the right of the Calculator label.
      And expression similar to
      rms(VT("/net14"))
      displays in the Expression field.
    3. In the Direction cyclic field, select >=
    4. In the Target field, enter 300m.
    5. In the Acceptable field, enter 10.
    6. Click the % within Target button.
    7. Verify that the Enabled button is active.
      The Adding Goals form looks like this.
    8. Click OK.
      The third goal is added to the Circuit Optimizer window.

Add the Circuit Variables to the Optimizer

Add the variables to the Circuit Optimizer window.

  1. In the Circuit Optimizer window, choose Variables – Add/Edit.
  2. When the Editing Variables form opens
    1. In the Name list box, click the lna_ip3 variable.
      The lna_ip3 variable is highlighted in the list box and it’s current value -5 displays in the Initial Value field.
    2. In the Minimum Value field, enter -9.
    3. In the Maximum Value field, enter 10.
    4. If necessary, click Enabled.
      The Editing Variables form appears as follows.
    5. Click Apply.

    Information for the lna_ip3 variable displays in the Variables section of the Circuit Optimizer.
  3. Repeat this procedure to add all the variables and values listed in Table 11-11

Variables and Values for the Optimizer

Variable Name Initial Value Minimum Value Maximum Value

lna_ip3

-5

-9

10

lna_gain

15

10

30

if_mx_gain

10

1

50

if_rbw

200m

50m

300m

rf_rbw

100m

50m

300m
  1. Click OK to close the Editing Variables form.
    In the Circuit Optimizer window, the variables and optimization goals appear as shown in Figure 11-14.
    Figure 11-14 Circuit Optimizer Setup

Run the Circuit Optimizer

This Circuit Optimizer analysis might take several hours to complete.
  1. In the Circuit Optimizer, choose Optimizer – Run n to display the Run for Fixed Number of Iterations form.
  2. In the Number of Iterations field, move the slider to the right until 12 displays.
  3. Click OK.
    The Run for Fixed Number of Iterations form closes and the Circuit Optimizer starts running.
    Watch for simulator startup messages in the CIW. Monitor the progress of the analysis in the log window.
    The waveform window opens when the first simulation completes. As simulations complete, the results are added to the plots in the waveform window.

Viewing the Circuit Optimizer Output

The Circuit Optimizer results displayed in the waveform window are shown in Figure 11-15.

Although the example is contrived, it illustrates the use model. After the Circuit Optimizer met the constraints it tried to minimize RMS noise.

  1. Save the initial state of the Analog Design Environment in case you want to start over.
  2. Then in the Circuit Optimizer window, click Results – Update Design. The last click updates the variables in the Analog Design Environment window with the last set of variables found by the Circuit Optimizer. You use these states in the passband view.

Summarizing the Design Procedure

To summarize, the semi-automated design procedure consists of

  1. Setting up the measurements
  2. Placing tolerances on the block parameters
  3. Constraining the system performance
  4. Identifying a quantity to minimize (or maximize)
  5. Running the Optimizer
  6. Evaluating the results

This is why the process is called semi-automated. After evaluating results for the first or second time you probably need to

  1. Refine tolerances
  2. Refine goals
  3. Add or delete constraints
  4. Add or delete variables

Each simulation covers 100s, or about 80 CDMA symbols. The suppressed carriers are an RF carrier at 2.14 GHz, an LO carrier at 2.354GHz, and an IF carrier at 214 MHz. The symbol rate is 1.2288 Mega-symbols per second.

Creating a Passband View of the Architectural Model

After you have designed an architecture, you can quickly create a passband view of the architectural model. (Currently, the passband behavioral models in the top_dwnPB category and in the passband view do not introduce any specifications that are not in the baseband models.)

The passband view checks for problems that might have escaped detection in the baseband view. For example, although the baseband view quickly assesses what filters do to the baseband signal, baseband models do not indicate whether the filters are indeed removing undesired carrier harmonics.

Baseband modeling is also not the best way to evaluate image rejection. Although the baseband model accurately simulates how the desired signal propagates through an image rejection receiver, it does not accurately simulate how much of the image signal propagates to the receiver output.

The passband view also creates a system testbench as mentioned in “Top-Down Design of RF Systems”.

Procedures for Creating the Passband Model of the Receiver

The procedures described in this section illustrate how to

Perform the following steps to create the passband model of the receiver:

  1. Copy the original receiver model from the Circuit Optimizer analysis to a new schematic window. Copy everything from the LNA to the low pass filters.
  2. Edit the properties of the IQ_demodulator (IQ_demod_BB) to set the last parameter, flo, to -frf+flo1 . The baseband view does not need the local oscillator frequency but the passband view does.
  3. Load the low pass filters with ports.
  4. Connect a port across the LNA_BB inputs. Set the Frequency name to fin, the frequency to frf, and the amplitude to power. (Do not abbreviate power to pwr because pwr is a reserved variable and you do not get any warning. SpectreRF may complain about a mysterious indexed undefined variable that increments from run to run.)
  5. Add loaded voltage-controlled-voltage sources as shown in Figure 11-16 to observe intermediate differential voltages.
    Figure 11-16 Passband View
  6. Check and save the schematic
  7. Close the schematic window.
  8. Bring up a Library Manager and select but do not open the schematic you just created.
  9. In the Library Manager window click File – New – Cell View.
  10. In the window that comes up, select Hierarchy Editor for the Tool. Click OK.
  11. Type in schematic for the View then click Use Template.
  12. Set the Name to Spectre.
  13. Enter veriloga_PB as the first item in the View List, then click OK.
  14. In the Hierarchy Editor window, click File – Save. This is important.
  15. Click the Open button to bring up the schematic.
  16. Bring up an Analog Design Environment tool and use the states from the last Circuit Optimizer iteration.
  17. Recall the states you saved from the last Circuit Optimizer iteration. Add the power variable and set it to -16.
  18. Delete the previous analyses and set up a PSS analysis. Enter a new Fundamental Tone named LO and make it 2.354GHz. Auto Calculate the Beat Frequency and type 1 for the Number of harmonics.
  19. Run the analysis and observe the intermediate differential voltages. The model is indeed now a passband model. At the higher power levels the LNA output contains odd harmonics of the RF carrier. The filter reflects the odd harmonics back to the LNA and does not let them propagate forward. The baseband model does not simulate the odd harmonics but it does simulate the intermodulation term between the second harmonic and fundamental that falls at the fundamental. One reason to simulate the passband view is to check for peak voltage levels that might exceed voltage ratings. The baseband models only simulate peak voltage at the carrier fundamental, not the absolute peak.
  20. Set up a swept PSS analysis. Sweep power from -32 to 0 in 10 steps.
  21. After the sweep finishes, click Results – Direct Plot in the Environment window, select Compression point, 1dB, Output Referred. Select the 0 harmonic because the end-to-end system produces a baseband output. Then click the port loading the top output low pass filter. You should see the compression point plot shown in Figure 11-17.
    Figure 11-17 End-to-end RF measurement, one dB compression point at the I-baseband output.
  22. Repeat the last step but this time click the lower output port. You should see the compression plot in Figure 11-18.
    Figure 11-18 End-to-end RF measurement, one dB compression point at the Q-baseband output.

Comparing Baseband and Passband Models

This section illustrates how to compare baseband and passband models by:

  1. Setting up a Transient analysis with the passband view
  2. Setting up a Transient analysis with the baseband view
  3. Directly comparing the baseband and passband models.

You run one analysis of the baseband view and two analyses of the passband view. You perform the second passband analysis with tightened tolerances.

  1. Save the passband schematic under a different name. You use the new copy.
  2. Repeat steps 9 through 17 from the last recipe for the new copy but do not enter the veriloga_PB view in the View List yet. You do a baseband analysis first.
  3. Delete the port driving the LNA.
  4. Delete the loaded voltage-controlled-voltage sources.
  5. You need to synthesize an antenna signal. Add an IQ_mod_BB from the top_dwnBB category. Set the I and Q gains to 0 dB. Set the 1dB compression points to 1000 so that the modulator is ideal. Instantiate it in front of the LNA with the pins aligned, then wire the pins straight across. Ground the phase_err pin.
  6. Drive the I_in pin of the IQ modulator with a port. Set the port frequency to 2MHz and name the frequency BB1. Set the amplitude to -16dBm.
  7. Do the same for the Q_in modulator input.
  8. Load or duplicate the states from the 12-iteration Circuit Optimizer analysis but delete the Noise and Transient analyses.
  9. Remove AM/PM conversion from the LNA by setting the last parameter in the properties list to zero.
    It is not fair to compare passband and baseband views with AM/PM conversion because the passband view does not capture it.
  10. Set up a 1us Transient analysis with default options.
  11. Run the analysis and plot the filtered baseband outputs, the outputs of the low pass filters.
    Note how fast the simulation runs. Save the results so you can plot them again later. 1
  12. Switch to the passband view by entering “veriloga_PB” in the View List in the Hierarchy Editor. Click the update button in the hierarchy editor.
  13. After you switch to the veriloga_PB view, edit the IQ modulator properties to set flo to frf. Edit the demodulator properties and set its flo to flo1-frf.
  14. Click Results – Printing Plotting Options then click the Overlay Plots button.
  15. Overlay the passband results with the baseband results. You see the waveforms in Figure 11-19. The comparison is not very good.
  16. Rerun the analysis with conservative options and set reltol to 1e-6. This run takes longer.
  17. Plot the results.
  18. Recall the saved baseband results and overlay them with those from the last simulation. You see the waveforms in Figure 11-20. The passband results now lay right on top of the baseband results but took much longer to compute! It was not obvious without the baseband results that the first passband simulation did not run with tight enough numerical tolerances.
    Figure 11-19 Passband and baseband results with default options in the passband analysis
    Figure 11-20 Passband and baseband results with tighter options in the passband analysis

Relationship Between Baseband and Passband Noise

Noise analysis at baseband can be confusing because factors of two appear in a number of places throughout the calculations. For example:

These questions are answered in this section.

Before sorting out the factors of two, note that baseband noise analysis is valid only for small signals. If any element in the architecture operates in a non-linear fashion, the noise analysis might be inaccurate. This is due to the fact that a baseband noise analysis follows a DC operating point analysis, rather than a PSS analysis.

Instantaneous incremental gain in a passband static non-linear model dithers at the carrier frequency.

The average gain is greater than the minimum gain. The baseband model remains in the non-linear region because it only simulates peak voltages. Consequently, the incremental gain is always a minimum and the baseband model under-estimates the amount of noise propagating to the output. If the peak input signal drives the model into saturation, be sure to scale the baseband noise results accordingly.

Introduction to Analysis

The circuit discussed here is called noise_test_circuit and you can find it in the rfExamples library. The circuit looks as shown in Figure 11-21.

Figure 11-21 The noise_test_circuit in the rfExamples Library

The noise_test_circuit shows the relationship between baseband and passband noise. One branch consists of passband models. The other branch is a baseband equivalent of the first. You can assess noise at each of three observation points located in each branch of the circuit. At each observation point, you can examine both the noise and pnoise summaries.

The I and Q inputs are both driven by the same DC source so that you only have to view one baseband output, the other baseband output is identical by symmetry. Noise parameters in the passband and baseband models are identical. Aside from the behavioral blocks at the end of each branch, each behavioral block has noise injected at its input.

Preparation Steps for Analyses

  1. Set up a PSS analysis.
    Because the local oscillator is inside the passband mixer models you have to manually enter the frequency (1GHz) into the PSS analysis form. Let the beat frequency be autocalculated and use 1 harmonic.
  2. Set up a pnoise analysis.
    Set the start frequency equal to 0 Hz, the stop frequency equal to 100MHz, use a linear sweep with 100 steps. Set the Maximum sideband to 1. For the input source select none and for the output use voltage. For the positive output node, select the I-input of the IQ_modulator in the passband branch. Use ground for the negative node.
  3. Set up a noise analysis.
    Sweep the frequency from 0 to 100MHz linearly in 100 steps. Use voltage for the output noise and select the I-input of the IQ_mod_BB component in the baseband branch for the positive node. Select ground for the negative node. Set the input noise port to any one of the ports in the circuit. Noise from that port does not affect either passband or baseband branches.
  4. Run the analysis.
  5. When the analysis finishes, go to the analog design environment simulation window and click results – print – pss noise summary.
  6. In the form that appears, include All types, set Type to integrated noise, look at noise from 0 to 100MHz, select truncate by number, and view the top 2 noise contributors.
    There are only 2 noise contributors at this point, noise at the I/Q inputs and noise from the low pass resistors.
  7. Print the noise summary (which is different from the pnoise summary).
    Again, print integrated noise (from 0 to 100MHz). Select All types and print noise from the top 2 noise contributors.
    Figure 11-22 shows the noise summaries. The two summaries agree because at this point in the circuit, both nodes are really baseband nodes.
    Figure 11-22 Noise Summaries for the First PSS pnoise and Noise Analyses
  8. Repeat the analyses.
    This time select the outi pins on the low pass filters as outputs in the appropriate noise analyses. Again print the same noise summaries but this time look at the top 12 noise contributors in each summary.
    Figure 11-23 shows the noise summaries for the second analysis. The top 7 noise contributors in the baseband and passband branches agree. The remaining noise contributors are negligible, and should be negligible for the circuit because it has no AM/PM conversion.
    Figure 11-23 Noise Summaries for the Second PSS pnoise Analyses
  9. Repeat the analysis again.
    This time change the Pnoise sweep to run from 900MHz to 1.1GHz in 200 linear steps and select the power amplifier output as the noise output node. For the noise analysis, leave the sweep at zero to 100MHz, use 100 steps as before, and change the output node to be the I-output of the power amplifier.
    Look at the top 7 noise contributors in each analysis. This time, integrate noise from 900MHz to 1.1GHz for the pnoise run and integrate noise from 0 to 100MHz for the noise run.
    Figure 11-24 shows the new summaries. Although the noise analyses agree at the ends of the branches, the noise analyses appear to disagree at a point where the baseband node is only a baseband equivalent, not a true baseband node.
    Figure 11-24 Noise Summaries for the Third PSS pnoise Analyses
    The apparent disagreement shown in Figure 11-24 requires an explanation. Let us examine the noise contributors and try to answer some the questions we posed earlier.

Noise at the power amplifier output due to noise injected at a passband node

Passband and baseband counterparts contribute the same amount of noise. However, in the baseband model, from symmetry you see the same numbers if you look at the Q-node. This means the baseband model predicts twice as much total noise due to noise injected between the modulators.

This factor of two is intentionally introduced to maintain the correct signal-to-noise ratio. The baseband model simulates peak signals; the carrier is suppressed. Without the carrier, signal power equals the square of the peak rather than one half of the square. This factor of two is not as arbitrary as it seems. The baseband model predicts the correct noise after demodulation because the passband demodulator model includes an extra factor of two to offset the factor of two inherent in the demodulation process.

Let the modulated carrier be i(t)*cos(wc*t) -q(t)*sin(wc*t) + noise(t).

Now consider the I-output. To generate the I-output, the demodulator multiplies the signal by cos(wc*t). The only part that propagates through the subsequent filter is (1/2)i(t) + noise(t)*cos(wc*t). To recover i(t), the passband demodulator model must scale this sum by two. (The baseband demodulator does not need to scale by two to extract the baseband signal because the carrier is suppressed.)

Thus, noise at passband demodulator model output equals 2*noise(t)*cos(wc*t). The filtered noise power density is then 4*(input noise density)/2. The factor of 1/2 comes from the cosine. The filtered output noise density is twice the input noise density.

In the baseband model, doubling the noise injected at the passband nodes was not simply a matter of convenience.

So, to answer questions 1 and 2,

Question 3 is rendered moot by using the noise summary and integrating over the proper band. If the pnoise analysis only integrated from 1GHz to 1.1GHz, (instead of from 900MHz to 1.1GHz), there would be a mysterious factor of two error.

In the baseband model, phase noise entering on the phase error pin propagates to both the I and Q outputs. In the baseband model, the same noise power appears on just the one output. Again, the total noise in the baseband model is twice that of the passband model to maintain the correct signal-to-noise ratio.

Noise injected at the modulator input (resistors and modulator noise)

Total noise in the baseband model due to modulator and input resistor noise is twice what it is from just one phase. Thus, the total noise due to sources on the input sides of the modulators differ by a factor of two. This occurs because the passband model is a real multiplier, which modulates the noise. If the peak signal voltage agrees with the baseband model, the passband modulator model attenuates input noise most of the time. The important thing is that the signal-to-noise ratios in the passband and baseband models agree anywhere in the system.

Now, copy the circuit, remove the capacitors at the modulator inputs, and repeat the last set of noise analyses. You see that in the passband model, the input resistors, R20 and R21, together contribute twice as much as the baseband counterpart, R22. With the capacitors, R20 and R21 together contribute just as much as R22. Without the capacitors, the input noise is truly white over the frequencies of interest. The same thing happens to the modulator noise itself. Figure 11-25 shows the results.

In particular, the modulator now also has noise at twice the carrier frequency and that noise mixes down to the carrier frequency. The baseband model is just that, a baseband model. The answer to question 4 is no. The baseband models do not account for noise, or signals, at carrier harmonics. The baseband equivalent noise analysis is valid only if noise injected into the modulators has no power beyond the local oscillator frequency. Phase noise injected at the phase noise pins should also be band limited.

Figure 11-25 Noise Summaries with the input capacitors removed.

  1. Note that the baseband outputs are out of phase with each other, even though the baseband inputs are in phase. In the baseband model, changing the RF-IF mixer LO from “flo1” to “-flo1” fixes the sign problem. In the passband model, the IQ_demodulator flo should be frf-flo1. To maintain the convention, in the baseband model the IF filter’s carrier frequency should be frf-flo1.

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