Product Documentation
Spectre FX Circuit Simulator User Guide
Product Version 23.1, September 2023

Dynamic Delay Check (dyn_delay)

Spectre Syntax

title dyn_delay node=[node] ref_node=[node] min_time=<value> max_time=<value> edge=[rise|fall|both] ref_edge=[rise|fall|both] vlth=<value> ref_vlth=<value> vhth=<value> ref_vhth=<value> time_window=[ start1 stop1 start2 stop2 .... ] <save=no|violation> <spice=no|yes> <subckt=[subckt1]> <fanout=all|gate|bulk> error_limit=<value>

SPICE Syntax

.cck title dyn_delay node=[node] ref_node=[node] min_time=<value> max_time=<value> edge=[rise|fall|both] ref_edge=[rise|fall|both] vlth=<value> ref_vlth=<value> vhth=<value> ref_vhth=<value> time_window=[ start1 stop1 start2 stop2 .... ] <save=no|violation> <spice=no|yes> <subckt=[subckt1]> <fanout=all|gate|bulk> error_limit=<value>

Description

Checks timing delays between two signals and reports nodes with edge delay errors.

The delay is measured between user-specified nodes and a reference node. A timing delay error occurs when the transition time of a signal falls outside the range of refTime + min_time and refTime + max_time, where refTime is the transition time of the reference signal. In other words, a timing delay error occurs when the delay between the signal and the reference signal is outside the range of min_time and max_time.

The ref_vhth and vhth parameters are used for triggering rising edge measurements, while ref_vlth and vlth parameters are used for triggering falling edge measurements. For example, a delay measurement from a rising reference signal to a falling signal includes measuring the delay from the time the reference signal crosses ref_vhth to the time the signal crosses vlth.

If the subckt parameter is specified, then node and ref_node are considered as local nodes to the specified subcircuit. In other words, node and ref_node belong to the instances of the specified subcircuit. Only one subckt value can be specified per check, with no wildcard.

If the subckt parameter is not specified, node and ref_node are considered as global nodes with hierarchical names starting from the top level.

The results are written to the dynamic.xml file, which can be viewed in a Web browser.

In the figure above, an error is reported if the signal net transition occurs outside the green marked area.

Arguments

node

Nodes to which the check is applied. Default is none.

ref_node

Name of the referenced node. Wildcards are not supported.

min_time

Minimum time delay between the signal and the reference signal transition. The specified value can be negative, 0, or positive.

max_time

Maximum time delay between the signal and the reference signal transition. The specified value can be negative, 0, or positive.

edge

Edge type of the signal net. Possible values are rise, fall, and both. Default value is rise.

ref_edge

Edge type of the reference signal. Possible values are rise, fall, and both. Default value is rise.

vlth

Low voltage threshold for the signal net.

ref_vlth

Low voltage threshold for the referenced net.

vhth

High voltage threshold for the signal net.

ref_vhth

High voltage threshold for the referenced net.

time_window

Time window to which the circuit check is applied. Multiple non-overlapping time windows are supported. Default time window is 0 to tend.

save

Specifies how to probe the signals specified within this circuit check. Possible values are:

  • no: None of the signals in this circuit check are probed. This is the default value.
  • violation: Automatically probe the signals with violations under this circuit check.

spice

Specifies whether to save the probed signals specified by the save parameter in the SPICE syntax.

Possible values are:

  • yes: Saves the signals in SPICE syntax
  • no: Saves the signals in Spectre syntax. This is the default value.

error_limit

Maximum number of errors reported. Default is 10000.

subckt

Instances of the specified subcircuit to which the check is applied. Default is none.

Example

Spectre Syntax

d1 dyn_delay ref_node=out8 node=out1 ref_edge=rise edge=fall min_time=100p max_time=5n time_window=[115n 200n]

SPICE Syntax

.cck d1 dyn_delay ref_node=out8 node=out1 ref_edge=rise edge=fall min_time=100p max_time=5n time_window=[115n 200n]

The above command reports any transition of signal data having delay of more than 5n seconds or having delay of less than 100p seconds. The delay is evaluated from the rising edge of out8 node to the falling edge of out1 node.

If the subckt parameter is not specified, then node and ref_node are considered as global nodes with the hierarchical names starting from the top level.

The following is an example of the report that is displayed on the Web browser:

Related Topics

Dynamic Checks


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